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H8/532 Hardware Manual
Preface
The H8/532 is a high-performance single-chip Hitachi-original microcomputer, featuring a highspeed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules. The H8/532 is an ideal microcontroller for a wide variety of medium-scale devices, including both office and industrial equipment and consumer products. Its highly orthogonal instruction set is designed for fast execution of programs coded in the highlevel C language. On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D converter, I/O ports, and other functions for compact implementation of high-performance application systems. The H8/532 is available in both a ZTATTM version* with on-chip PROM, ideal for the early stages of production or for products with frequently-changing specifications, and a masked-ROM version suitable for volume production. This manual gives a hardware description of the H8/532. For details of the instruction set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500 Series. * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.
Contents
Section 1 Overview
1.1 1.2 1.3 Features **********************************************************************************************************************************1 Block Diagram ***********************************************************************************************************************4 Pin Arrangements and Functions *******************************************************************************************5 1.3.1 Pin Arrangement *********************************************************************************************************5 1.3.2 Pin Functions **************************************************************************************************************8
Section 2 MCU Operating Modes and Address Space
2.1 2.2 2.3 Overview ******************************************************************************************************************************23 Mode Descriptions ***************************************************************************************************************24 Address Space Map **************************************************************************************************************25 2.3.1 Page Segmentation ****************************************************************************************************25 2.3.2 Page 0 Address Allocations **************************************************************************************27 Mode Control Register (MDCR) *****************************************************************************************29
2.4
Section 3 CPU
3.1 Overview ******************************************************************************************************************************31 3.1.1 Features *********************************************************************************************************************31 3.1.2 Address Space ***********************************************************************************************************32 3.1.3 Register Configuration **********************************************************************************************33 CPU Register Descriptions **************************************************************************************************34 3.2.1 General Registers ******************************************************************************************************34 3.2.2 Control Registers ******************************************************************************************************35 3.2.3 Initial Register Values ***********************************************************************************************40 Data Formats ************************************************************************************************************************41 3.3.1 Data Formats in General Registers ***************************************************************************41 3.3.2 Data Formats in Memory ******************************************************************************************42 Instructions ***************************************************************************************************************************44 3.4.1 Basic Instruction Formats *****************************************************************************************44 3.4.2 Addressing Modes ****************************************************************************************************45 3.4.3 Effective Address Calculation ***********************************************************************************47 Instruction Set **********************************************************************************************************************50 3.5.1 Overview *******************************************************************************************************************50 3.5.2 Data Transfer Instructions *****************************************************************************************52 3.5.3 Arithmetic Instructions *********************************************************************************************53 3.5.4 Logic Operations *******************************************************************************************************54 3.5.5 Shift Operations ********************************************************************************************************55 3.5.6 Bit Manipulations ******************************************************************************************************56 3.5.7 Branching Instructions **********************************************************************************************57
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.5.8 System Control Instructions **************************************************************************************59 3.5.9 Short-Format Instructions *****************************************************************************************62 Operating Modes ******************************************************************************************************************62 3.6.1 Minimum Mode ********************************************************************************************************62 3.6.2 Maximum Mode ********************************************************************************************************63 Basic Operational Timing ****************************************************************************************************63 3.7.1 Overview *******************************************************************************************************************63 3.7.2 On-Chip Memory Access Cycle *******************************************************************************64 3.7.3 Pin States during On-Chip Memory Access *************************************************************65 3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) ***********************************66 3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) *****************67 3.7.6 External Access Cycle ***********************************************************************************************68 CPU States ***************************************************************************************************************************69 3.8.1 Overview *******************************************************************************************************************69 3.8.2 Program Execution State *******************************************************************************************71 3.8.3 Exception-Handling State *****************************************************************************************71 3.8.4 Bus-Released State ****************************************************************************************************72 3.8.5 Reset State *****************************************************************************************************************77 3.8.6 Power-Down State ****************************************************************************************************77 Programming Notes *************************************************************************************************************78 3.9.1 Restriction on Address Location *******************************************************************************78 3.9.2 Note on MULXU Instruction*************************************************************************************79
Section 4 Exception Handling
4.1 Overview ******************************************************************************************************************************81 4.1.1 Types of Exception Handling and Their Priority ******************************************************81 4.1.2 Hardware Exception-Handling Sequence *****************************************************************82 4.1.3 Exception Factors and Vector Table **************************************************************************82 Reset ************************************************************************************************************************************85 4.2.1 Overview *******************************************************************************************************************85 4.2.2 Reset Sequence *********************************************************************************************************85 4.2.3 Stack Pointer Initialization ****************************************************************************************86 Address Error ***********************************************************************************************************************89 4.3.1 Illegal Instruction Prefetch ****************************************************************************************89 4.3.2 Word Data Access at Odd Address ***************************************************************************89 4.3.3 Off-Chip Address Access in Single-Chip Mode *******************************************************89 Trace ************************************************************************************************************************************90 Interrupts ******************************************************************************************************************************90 Invalid Instruction ****************************************************************************************************************92 Trap Instructions and Zero Divide ***************************************************************************************92 Cases in Which Exception Handling is Deferred *****************************************************************92
4.2
4.3
4.4 4.5 4.6 4.7 4.8
4.8.1 Instructions that Disable Interrupts ***************************************************************************92 4.8.2 Disabling of Exceptions Immediately after a Reset **************************************************93 4.8.3 Disabling of Interrupts after a Data Transfer Cycle **************************************************93 4.9 Stack Status after Completion of Exception Handling ********************************************************94 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions ***************************************96 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions **********************************************************************************************96 4.10 Notes on Use of the Stack ****************************************************************************************************96
Section 5 Interrupt Controller
5.1 Overview ******************************************************************************************************************************97 5.1.1 Features *********************************************************************************************************************97 5.1.2 Block Diagram **********************************************************************************************************98 5.1.3 Register Configuration **********************************************************************************************99 Interrupt Types *********************************************************************************************************************99 5.2.1 External Interrupts ****************************************************************************************************99 5.2.2 Internal Interrupts ****************************************************************************************************101 5.2.3 Interrupt Vector Table *********************************************************************************************101 Register Descriptions *********************************************************************************************************103 5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) ***********************************************103 5.3.2 Timing of Priority Setting ***************************************************************************************104 Interrupt Handling Sequence *********************************************************************************************104 5.4.1 Interrupt Handling Flow ******************************************************************************************104 5.4.2 Stack Status after Interrupt Handling Sequence *****************************************************107 5.4.3 Timing of Interrupt Exception-Handling Sequence ************************************************108 Interrupts During Operation of the Data Transfer Controller ********************************************108 Interrupt Response Time ****************************************************************************************************111
5.2
5.3
5.4
5.5 5.6
Section 6 Data Transfer Controller
6.1 Overview ****************************************************************************************************************************113 6.1.1 Features *******************************************************************************************************************113 6.1.2 Block Diagram ********************************************************************************************************113 6.1.3 Register Configuration ********************************************************************************************114 Register Descriptions *********************************************************************************************************115 6.2.1 Data Transfer Mode Register (DTMR) *******************************************************************115 6.2.2 Data Transfer Source Address Register (DTSR) ****************************************************116 6.2.3 Data Transfer Destination Register (DTDR) *********************************************************116 6.2.4 Data Transfer Count Register (DTCR) *******************************************************************116 6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) *************************************117 Data Transfer Operation *****************************************************************************************************118
6.2
6.3
6.4 6.5
6.3.1 Data Transfer Cycle ************************************************************************************************118 6.3.2 DTC Vector Table ***************************************************************************************************120 6.3.3 Location of Register Information in Memory *********************************************************122 6.3.4 Length of Data Transfer Cycle ********************************************************************************122 Procedure for Using the DTC ********************************************************************************************124 Example *****************************************************************************************************************************125
Section 7 Wait-State Controller
7.1 Overview ****************************************************************************************************************************127 7.1.1 Features *******************************************************************************************************************127 7.1.2 Block Diagram ********************************************************************************************************128 7.1.3 Register Configuration ********************************************************************************************128 Wait-State Control Register ***********************************************************************************************129 Operation in Each Wait Mode ********************************************************************************************130 7.3.1 Programmable Wait Mode **************************************************************************************130 7.3.2 Pin Wait Mode ********************************************************************************************************131 7.3.3 Pin Auto-Wait Mode ***********************************************************************************************133
7.2 7.3
Section 8 Clock Pulse Generator
8.1 8.2 8.3 Overview ****************************************************************************************************************************135 8.1.1 Block Diagram ********************************************************************************************************135 Oscillator Circuit ****************************************************************************************************************135 System Clock Divider ********************************************************************************************************138
Section 9 I/O Ports
9.1 9.2 Overview ****************************************************************************************************************************139 Port 1 **********************************************************************************************************************************142 9.2.1 Overview *****************************************************************************************************************142 9.2.2 Port 1 Registers *******************************************************************************************************142 9.2.3 Pin Functions in Each Mode ***********************************************************************************145 Port 2 **********************************************************************************************************************************148 9.3.1 Overview *****************************************************************************************************************148 9.3.2 Port 2 Registers *******************************************************************************************************149 9.3.3 Pin Functions in Each Mode ***********************************************************************************150 Port 3 **********************************************************************************************************************************151 9.4.1 Overview *****************************************************************************************************************151 9.4.2 Port 3 Registers *******************************************************************************************************152 9.4.3 Pin Functions in Each Mode ***********************************************************************************153 Port 4 **********************************************************************************************************************************154 9.5.1 Overview *****************************************************************************************************************154 9.5.2 Port 4 Registers *******************************************************************************************************155
9.3
9.4
9.5
9.5.3 9.6 Port 5 9.6.1 9.6.2 9.6.3 9.6.4 9.7 Port 6 9.7.1 9.7.2 9.7.3 9.7.4 9.8 Port 7 9.8.1 9.8.2 9.8.3 9.9 Port 8 9.9.1 9.9.2 9.10 Port 9 9.10.1 9.10.2 9.10.3
Pin Functions in Each Mode ***********************************************************************************156 **********************************************************************************************************************************157 Overview *****************************************************************************************************************157 Port 5 Registers *******************************************************************************************************158 Pin Functions in Each Mode ***********************************************************************************159 Built-in MOS Pull-Up *********************************************************************************************161 **********************************************************************************************************************************163 Overview *****************************************************************************************************************163 Port 6 Registers *******************************************************************************************************164 Pin Functions in Each Mode ***********************************************************************************165 Built-in MOS Pull-Up *********************************************************************************************167 **********************************************************************************************************************************167 Overview *****************************************************************************************************************167 Port 7 Registers *******************************************************************************************************168 Pin Functions **********************************************************************************************************169 **********************************************************************************************************************************172 Overview *****************************************************************************************************************172 Port 8 Registers *******************************************************************************************************172 **********************************************************************************************************************************173 Overview *****************************************************************************************************************173 Port 9 Registers *******************************************************************************************************173 Pin Functions **********************************************************************************************************174
Section 10 16-Bit Free-Running Timers
10.1 Overview ****************************************************************************************************************************177 10.1.1 Features *******************************************************************************************************************177 10.1.2 Block Diagram ********************************************************************************************************178 10.1.3 Input and Output Pins *********************************************************************************************179 10.1.4 Register Configuration ********************************************************************************************180 10.2 Register Descriptions *********************************************************************************************************181 10.2.1 Free-Running Counter (FRC) - H'FF92, H'FFA2, H'FFB2 ************************************181 10.2.2 Output Compare Registers A and B (OCRA and OCRB) - H'FF94 and H'FF96, H'FFA4 and H'FFA6, H'FFB4 and H'FFB6 ***************************************182 10.2.3 Input Capture Register (ICR) - H'FF98, H'FFA8, H'FFB8 *************************************182 10.2.4 Timer Control Register (TCR) ********************************************************************************183 10.2.5 Timer Control/Status Register (TCSR) *******************************************************************185 10.3 CPU Interface *********************************************************************************************************************188 10.4 Operation ****************************************************************************************************************************190 10.4.1 FRC Incrementation Timing ***********************************************************************************190 10.4.2 Output Compare Timing *****************************************************************************************191 10.4.3 Input Capture Timing **********************************************************************************************193
10.5 10.6
10.7 10.8
10.4.4 Setting of FRC Overflow Flag (OVF) *********************************************************************195 CPU Interrupts and DTC Interrupts ***********************************************************************************195 Synchronization of Free-Running Timers 1 to 3 ****************************************************************196 10.6.1 Synchronization after a Reset *********************************************************************************196 10.6.2 Synchronization by Writing to FRCs **********************************************************************196 Sample Application ************************************************************************************************************200 Application Notes **************************************************************************************************************200
Section 11 8-Bit Timer
11.1 Overview ****************************************************************************************************************************207 11.1.1 Features *******************************************************************************************************************207 11.1.2 Block Diagram ********************************************************************************************************208 11.1.3 Input and Output Pins *********************************************************************************************209 11.1.4 Register Configuration ********************************************************************************************209 11.2 Register Descriptions *********************************************************************************************************209 11.2.1 Timer Counter (TCNT) - H'FFD4 ***************************************************************************209 11.2.2 Time Constant Registers A and B (TCORA and TCORB) - H'FFD2 and H'FFD3 ******************************************************210 11.2.3 Timer Control Register (TCR) - H'FFD0 ****************************************************************210 11.2.4 Timer Control/Status Register (TCSR) *******************************************************************212 11.3 Operation ****************************************************************************************************************************214 11.3.1 TCNT Incrementation Timing ********************************************************************************214 11.3.2 Compare Match Timing ******************************************************************************************215 11.3.3 External Reset of TCNT *****************************************************************************************217 11.3.4 Setting of TCNT Overflow Flag *****************************************************************************218 11.4 CPU Interrupts and DTC Interrupts ***********************************************************************************218 11.5 Sample Application ************************************************************************************************************219 11.6 Application Notes **************************************************************************************************************220
Section 12 PWM Timer
12.1 Overview ****************************************************************************************************************************227 12.1.1 Features *******************************************************************************************************************227 12.1.2 Block Diagram ********************************************************************************************************227 12.1.3 Input and Output Pins *********************************************************************************************228 12.1.4 Register Configuration ********************************************************************************************229 12.2 Register Descriptions *********************************************************************************************************229 12.2.1 Timer Counter (TCNT) - H'FFC2, H'FFC4, H'FFCA ********************************************229 12.2.2 Duty Register (DTR) - H'FFC1, H'FFC5, H'FFC9 *************************************************230 12.2.3 Timer Control Register (TCR) - H'FFC0, H'FFC4, H'FFC8 **********************************230 12.3 Operation ****************************************************************************************************************************232 12.4 Application Notes **************************************************************************************************************234
Section 13 Watchdog Timer
13.1 Overview ****************************************************************************************************************************235 13.1.1 Features *******************************************************************************************************************235 13.1.2 Block Diagram ********************************************************************************************************236 13.1.3 Register Configuration ********************************************************************************************236 13.2 Register Descriptions *********************************************************************************************************237 13.2.1 Timer Counter TCNT - H'FFED *****************************************************************************237 13.2.2 Timer Control/Status Register (TCSR) - H'FFEC (Read), H'FFED (Write) **********237 13.2.3 Notes on Register Access ****************************************************************************************239 13.3 Operation ****************************************************************************************************************************240 13.3.1 Watchdog Timer Mode *******************************************************************************************240 13.3.2 Interval Timer Mode ***********************************************************************************************241 13.3.3 Operation in Software Standby Mode *********************************************************************242 13.3.4 Setting of Overflow Flag *****************************************************************************************243 13.4 Application Notes **************************************************************************************************************243
Section 14 Serial Communication Interface
14.1 Overview ****************************************************************************************************************************245 14.1.1 Features *******************************************************************************************************************245 14.1.2 Block Diagram ********************************************************************************************************246 14.1.3 Input and Output Pins *********************************************************************************************247 14.1.4 Register Configuration ********************************************************************************************247 14.2 Register Descriptions *********************************************************************************************************247 14.2.1 Receive Shift Register (RSR) **********************************************************************************247 14.2.2 Receive Data Register (RDR) - H'FFDD ****************************************************************248 14.2.3 Transmit Shift Register (TSR) ********************************************************************************248 14.2.4 Transmit Data Register (TDR) - H'FFDB ***************************************************************248 14.2.5 Serial Mode Register (SMR) - H'FFD8 ******************************************************************249 14.2.6 Serial Control Register (SCR) - H'FFDA ***************************************************************251 14.2.7 Serial Status Register (SSR) - H'FFDC ******************************************************************253 14.2.8 Bit Rate Register (BRR) - H'FFD9 *************************************************************************255 14.3 Operation ****************************************************************************************************************************259 14.3.1 Overview *****************************************************************************************************************259 14.3.2 Asynchronous Mode ***********************************************************************************************260 14.3.3 Synchronous Mode *************************************************************************************************264 14.4 CPU Interrupts and DTC Interrupts ***********************************************************************************268 14.5 Application Notes **************************************************************************************************************269
Section 15 A/D Converter
15.1 Overview ****************************************************************************************************************************273
15.2
15.3 15.4
15.5 15.6
15.1.1 Features *******************************************************************************************************************273 15.1.2 Block Diagram ********************************************************************************************************274 15.1.3 Input Pins ****************************************************************************************************************275 15.1.4 Register Configuration ********************************************************************************************275 Register Descriptions *********************************************************************************************************276 15.2.1 A/D Data Registers (ADDR) - H'FFE0 to H'FFE7 *************************************************276 15.2.2 A/D Control/Status Register (ADCSR) - H'FFE8 **************************************************277 CPU Interface *********************************************************************************************************************279 Operation ****************************************************************************************************************************280 15.4.1 Single Mode ************************************************************************************************************281 15.4.2 Scan Mode **************************************************************************************************************284 Input Sampling Time and A/D Conversion Time ***************************************************************287 Interrupts and the Data Transfer Controller ***********************************************************************289
Section 16 RAM
16.1 Overview ****************************************************************************************************************************291 16.1.1 Block Diagram ********************************************************************************************************291 16.1.2 Register Configuration ********************************************************************************************292 16.2 RAM Control Register (RAMCR) *************************************************************************************292 16.3 Operation ****************************************************************************************************************************292 16.3.1 Expanded Modes (Modes 1, 2, 3, and 4) ****************************************************************292 16.3.2 Single-Chip Mode (Mode 7) ***********************************************************************************293
Section 17 ROM
17.1 Overview ****************************************************************************************************************************295 17.1.1 Block Diagram ********************************************************************************************************295 17.2 PROM Modes *********************************************************************************************************************296 17.2.1 PROM Mode Setup *************************************************************************************************296 17.2.2 Socket Adapter Pin Arrangements and Memory Map ********************************************297 17.3 Programming **********************************************************************************************************************299 17.3.1 Writing and Verifying *********************************************************************************************299 17.3.2 Notes on Writing *****************************************************************************************************302 17.3.3 Reliability of Written Data **************************************************************************************303 17.3.4 Erasing of Data *******************************************************************************************************304 17.4 Handling of Windowed Packages **************************************************************************************304
Section 18 Power-Down State
18.1 Overview ****************************************************************************************************************************307 18.2 Sleep Mode ************************************************************************************************************************308 18.2.1 Transition to Sleep Mode ****************************************************************************************308 18.2.2 Exit from Sleep Mode *********************************************************************************************308
18.3 Software Standby Mode *****************************************************************************************************308 18.3.1 Transition to Software Standby Mode ********************************************************************308 18.3.2 Software Standby Control Register (SBYCR) ********************************************************309 18.3.3 Exit from Software Standby Mode *************************************************************************310 18.3.4 Sample Application of Software Standby Mode ****************************************************310 18.3.5 Application Notes ***************************************************************************************************311 18.4 Hardware Standby Mode ****************************************************************************************************312 18.4.1 Transition to Hardware Standby Mode *******************************************************************312 18.4.2 Recovery from Hardware Standby Mode ***************************************************************312 18.4.3 Timing Sequence of Hardware Standby Mode *******************************************************313
Section 19 E Clock Interface
19.1 Overview ****************************************************************************************************************************315
Section 20 Electrical Specifications
20.1 Absolute Maximum Ratings **********************************************************************************************319 20.2 Electrical Characteristics ****************************************************************************************************319 20.2.1 DC Characteristics **************************************************************************************************319 20.2.2 AC Characteristics **************************************************************************************************322 20.2.3 A/D Converter Characteristics ********************************************************************************326 20.3 MCU Operatinal Timing ****************************************************************************************************326 20.3.1 Bus Timing **************************************************************************************************************327 20.3.2 Control Signal Timing ********************************************************************************************330 20.3.3 Clock Timing **********************************************************************************************************331 20.3.4 I/O Port Timing *******************************************************************************************************333 20.3.5 16-Bit Free-Running Timer Timing ************************************************************************334 20.3.6 8-Bit Timer Timing *************************************************************************************************335 20.3.7 Pulse Width Modulation Timer Timing ******************************************************************336 20.3.8 Serial Communication Interface Timing *****************************************************************336
Appendix A Instructions
A.1 A.2 A.3 A.4 Instruction Set ********************************************************************************************************************337 Instruction Codes ***************************************************************************************************************342 Operation Code Map **********************************************************************************************************353 Instruction Execution Cycles *********************************************************************************************358 A.4.1 Calculation of Instruction Execution States ************************************************************358 A.4.2 Tables of Instruction Execution Cycles ******************************************************************359
Appendix B Register Field
B.1 B.2 Register Addresses and Bit Names ************************************************************************************367 Register Descriptions *********************************************************************************************************372
Appendix C I/O Port Schematic Diagrams
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Schematic Diagram of Port 1 Schematic Diagram of Port 2 Schematic Diagram of Port 3 Schematic Diagram of Port 4 Schematic Diagram of Port 5 Schematic Diagram of Port 6 Schematic Diagram of Port 7 Schematic Diagram of Port 8 Schematic Diagram of Port 9 *********************************************************************************************407 *********************************************************************************************413 *********************************************************************************************414 *********************************************************************************************415 *********************************************************************************************416 *********************************************************************************************417 *********************************************************************************************418 *********************************************************************************************423 *********************************************************************************************424
Appendix D Memory Map *************************************************************************************************429 Appendix E Pin State
E.1 E.2 Port State of Each Pin State ***********************************************************************************************431 Pin Stattus in the Reset State **********************************************************************************************434
Appendix F Timing of Entry to and Recovery from Hardware Standby Mode ********449 Appendix G Package Dimensions ************************************************************************************451
Figures
1-1 1-2 1-3 1-4 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 (a) 3-10 (b) 3-11 3-12 3-13 3-14 3-15 4-1 4-2 4-3 4-4 4-5 5-1 5-2 5-3 (a) 5-3 (b) 5-4 5-5 6-1 6-2 6-3 6-4 6-5 6-6 7-1 Block Diagram *******************************************************************************************************************4 Pin Arrangement (CP-84, Top View) *********************************************************************************5 Pin Arrangement (CG-84, Top View) ********************************************************************************6 Pin Arrangement (FP-80A, Top View) ******************************************************************************7 Address Space in Each Mode ******************************************************************************************26 Map of Page 0 ******************************************************************************************************************28 CPU Operating Modes *****************************************************************************************************32 Registers in the CPU ********************************************************************************************************33 Stack Pointer ********************************************************************************************************************34 Combinations of Page Registers with Other Registers ****************************************************38 Short Absolute Addressing Mode and Base Register ******************************************************39 On-Chip Memory Access Timing ************************************************************************************64 Pin States during Access to On-Chip Memory ****************************************************************65 Register Field Access Timing ******************************************************************************************66 Pin States during Register Field Access **************************************************************************67 External Access Cycle (Read Access) *****************************************************************************68 External Access Cycle (Write Access) ****************************************************************************69 Operating States ***************************************************************************************************************70 State Transitions **************************************************************************************************************71 Bus-Right Release Cycle (During On-chip Memory Access Cycle) *******************************73 Bus-Right Release Cycle (During External Access Cycle) *********************************************74 Bus-Right Release Cycle (During Internal CPU Operation) *******************************************75 Types of Factors Causing Exception Handling ****************************************************************83 Reset Vector *********************************************************************************************************************86 Reset Sequence (Minimum Mode, On-Chip Memory) ***************************************************87 Reset Sequence (Maximum Mode, External Memory) ***************************************************88 Interrupt Sources (and Number of Interrupt Types) ********************************************************91 Interrupt Controller Block Diagram ********************************************************************************98 Interrupt Handling Flowchart ****************************************************************************************106 Stack before and after Interrupt Exception-Handling (Minimum Mode) **********************107 Stack before and after Interrupt Exception-Handling (Maximum Mode) *********************108 Interrupt Sequence (Minimum Mode, On-Chip Memory) ********************************************109 Interrupt Sequence (Maximum Mode, External Memory) ********************************************110 Block Diagram of Data Transfer Controller ******************************************************************114 Flowchart of Data Transfer Cycle **********************************************************************************119 DTC Vector Table **********************************************************************************************************120 DTC Vector Table Entry ************************************************************************************************121 Order of Register Information ***************************************************************************************122 Use of DTC to Receive Data via Serial Communication Interface *******************************126 Block Diagram of Wait-State Controller ***********************************************************************128
7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 10-1 10-2 (a) 10-2 (b) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10
Programmable Wait Mode *********************************************************************************************131 Pin Wait Mode ***************************************************************************************************************132 Pin Auto-Wait Mode ******************************************************************************************************133 Block Diagram of Clock Pulse Generator *********************************************************************135 Connection of Crystal Oscillator (Example) *****************************************************************136 Crystal Oscillator Equivalent Circuit *****************************************************************************136 Notes on Board Design around External Crystal ***********************************************************137 External Clock Input (Example) ************************************************************************************137 Phase Relationship of o Clock and E clock *******************************************************************138 Pin Functions of Port 1 **************************************************************************************************142 Pin Functions of Port 2 **************************************************************************************************148 Port 2 Pin Functions in Expanded Modes **********************************************************************150 Port 2 Pin Functions in Single-Chip Mode ********************************************************************151 Pin Functions of Port 3 **************************************************************************************************151 Port 3 Pin Functions in Expanded Modes **********************************************************************153 Port 3 Pin Functions in Single-Chip Mode ********************************************************************154 Pin Functions of Port 4 **************************************************************************************************154 Port 4 Pin Functions in Expanded Modes **********************************************************************156 Port 4 Pin Functions in Single-Chip Mode ********************************************************************157 Pin Functions of Port 5 **************************************************************************************************157 Port 5 Pin Functions in Modes 1 and 3 **************************************************************************159 Port 5 Pin Functions in Modes 2 and 4 **************************************************************************160 Port 5 Pin Functions in Single-Chip Mode ********************************************************************160 Pin Functions of Port 6 **************************************************************************************************164 Port 6 Pin Functions in Mode 3 *************************************************************************************166 Port 6 Pin Functions in Mode 4 *************************************************************************************166 Port 6 Pin Functions in Modes 7, 2, and 1 *********************************************************************167 Pin Functions of Port 7 **************************************************************************************************168 Pin Functions of Port 8 **************************************************************************************************172 Pin Functions of Port 9 **************************************************************************************************173 Block Diagram of 16-Bit Free-Running Timer *************************************************************178 Write Access to FRC (When CPU Writes H'AA55) *****************************************************189 Read Access to FRC (When FRC Contains H'AA55) ***************************************************190 Increment Timing for External Clock Input ******************************************************************191 Setting of Output Compare Flags **********************************************************************************192 Timing of Output Compare A ****************************************************************************************192 Clearing of FRC by Compare-Match A *************************************************************************193 Input Capture Timing (Usual Case) *******************************************************************************193 Input Capture Timing (1-State Delay) ***************************************************************************194 Setting of Input Capture Flag ****************************************************************************************194 Setting of Overflow Flag (OVF) ************************************************************************************195
10-11 10-12 10-13 10-14 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 14-3 14-4 14-5 15-1 15-2 15-3 15-4 15-5 16-1 17-1 17-2 17-3 17-4 17-5 17-6 18-1
Square-Wave Output (Example) ************************************************************************************200 FRC Write-Clear Contention *****************************************************************************************201 FRC Write-Increment Contention *********************************************************************************202 Contention between OCR Write and Compare-Match **************************************************203 Block Diagram of 8-Bit Timer ***************************************************************************************208 Count Timing for External Clock Input *************************************************************************215 Setting of Compare-Match Flags ***********************************************************************************216 Timing of Timer Output *************************************************************************************************216 Timing of Compare-Match Clear **********************************************************************************217 Timing of External Reset ***********************************************************************************************217 Setting of Overflow Flag (OVF) ************************************************************************************218 Example of Pulse Output ***********************************************************************************************219 TCNT Write-Clear Contention **************************************************************************************220 TCNT Write-Increment Contention ******************************************************************************221 Contention between TCOR Write and Compare-Match ***********************************************222 Block Diagram of PWM Timer *************************************************************************************228 PWM Timing *****************************************************************************************************************233 Block Diagram of Timer Counter **********************************************************************************236 Writing to TCNT and TCSR ******************************************************************************************239 Operation in Watchdog Timer Mode *****************************************************************************241 Operation in Interval Timer Mode *********************************************************************************242 Setting of OVF Bit *********************************************************************************************************243 TCNT Write-Increment Contention ******************************************************************************244 Block Diagram of Serial Communication Interface ******************************************************246 Data Format in Asynchronous Mode *****************************************************************************260 Phase Relationship between Clock Output and Transmit Data *************************************261 Data Format in Synchronous Mode *******************************************************************************265 Sampling Timing (Asynchronous Mode) **********************************************************************271 Block Diagram of A/D Converter **********************************************************************************274 Read Access to A/D Data Register (When Register Contains H'AA40) ***********************280 A/D Operation in Single Mode (When Channel 1 is Selected) *************************************283 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) *****************************286 A/D Conversion Timing *************************************************************************************************288 Block Diagram of On-Chip RAM *********************************************************************************291 Block Diagram of On-Chip ROM *********************************************************************************296 Socket Adapter Pin Arrangements *********************************************************************************298 Memory Map in PROM Mode ***************************************************************************************299 High-Speed Programming Flowchart ****************************************************************************300 PROM Write/Verify Timing ******************************************************************************************302 Recommended Screening Procedure *****************************************************************************303 NMI Timing of Software Standby Mode (Application Example) *********************************311
18-2 19-1 19-2 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 C-1 (a) C-1 (b) C-1 (c) C-1 (d) C-1 (e) C-1 (f) C-1 (g) C-2 C-3 C-4 C-5 C-6 C-7 (a) C-7 (b) C-7 (c)
Hardware Standby Sequence *****************************************************************************************313 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Maximum Synchronization Delay) ******************************************************************************316 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Minimum Synchronization Delay) *******************************************************************************317 Example of Circuit for Driving a Darlington Transistor Pair ****************************************322 Example of Circuit for Driving an LED ************************************************************************322 Output Load Circuit *******************************************************************************************************325 Basic Bus Cycle (without Wait States) in Expanded Modes *****************************************327 Basic Bus Cycle (with 1 Wait State) in Expanded Modes *********************************************328 Bus Cycle Synchronized with E Clock **************************************************************************329 Reset Input Timing ******************************************************************************************************** 330 Interrupt Input Timing ***************************************************************************************************330 NMI Pulse Width (for Recovery from Software Standby Mode) **********************************330 Bus Release State Timing **********************************************************************************************331 E Clock Timing **************************************************************************************************************331 Clock Oscillator Stabilization Timing ***************************************************************************332 I/O Port Input/Output Timing ****************************************************************************************333 Free-Running Timer Input/Output Timing ********************************************************************334 External Clock Input Timing for Free-Running Timers ************************************************334 8-Bit Timer Output Timing ********************************************************************************************335 8-Bit Timer Clock Input Timing ************************************************************************************335 8-Bit Timer Reset Input Timing ************************************************************************************335 PWM Timer Output Timing ******************************************************************************************336 SCI Input Clock Timing ************************************************************************************************336 SCI Input/Output Timing (Synchronous Mode) ************************************************************336 Schematic Diagram of Port 1, Pin P10 **************************************************************************407 Schematic Diagram of Port 1, Pin P11 **************************************************************************407 Schematic Diagram of Port 1, Pin P12 ***************************************************************************408 Schematic Diagram of Port 1, Pin P13 **************************************************************************409 Schematic Diagram of Port 1, Pin P14 ***************************************************************************410 Schematic Diagram of Port 1, Pins P15 and P16 ***********************************************************411 Schematic Diagram of Port 1, Pin P17 **************************************************************************412 Schematic Diagram of Port 2 *****************************************************************************************413 Schematic Diagram of Port 3 *****************************************************************************************414 Schematic Diagram of Port 4 *****************************************************************************************415 Schematic Diagram of Port 5 *****************************************************************************************416 Schematic Diagram of Port 6 *****************************************************************************************417 Schematic Diagram of Port 7, Pin P70 **************************************************************************418 Schematic Diagram of Port 7, Pins P71 and P72 ***********************************************************419 Schematic Diagram of Port 7, Pin P73 **************************************************************************420
C-7 (d) C-7 (e) C-8 C-9 (a) C-9 (b) C-9 (c) C-9 (d) C-9 (e) E-1 E-2 E-3 E-4 E-5 E-6 E-7 E-8 E-9 E-10 G-1 G-2 G-3
Schematic Diagram of Port 7, Pins P74, P75 and P76 ****************************************************421 Schematic Diagram of Port 7, Pin P77 **************************************************************************422 Schematic Diagram of Port 8 *****************************************************************************************423 Schematic Diagram of Port 9, Pins P90 and P91 ***********************************************************424 Schematic Diagram of Port 9, Pins P92, P93 and P94 ****************************************************425 Schematic Diagram of Port 9, Pin P95 **************************************************************************426 Schematic Diagram of Port 9, Pin P96 **************************************************************************427 Schematic Diagram of Port 9, Pin P97 **************************************************************************428 Reset during Memory Access (Mode 1) ************************************************************************435 Reset during Memory Access (Mode 1) ************************************************************************436 Reset during Memory Access (Mode 2) ************************************************************************438 Reset during Memory Access (Mode 2) ************************************************************************439 Reset during Memory Access (Mode 3) ************************************************************************441 Reset during Memory Access (Mode 3) ************************************************************************442 Reset during Memory Access (Mode 4) ************************************************************************444 Reset during Memory Access (Mode 4) ************************************************************************445 Reset during Memory Access (Mode 7) ************************************************************************446 Reset during Memory Access (Mode 7) ************************************************************************447 Package Dimensions (CP-84) ****************************************************************************************451 Package Dimensions (CG-84) ***************************************************************************************451 Package Dimensions (FP-80A) **************************************************************************************452
Tables
1-1 1-2 1-3 1-4 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 Features ******************************************************************************************************************************2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) *******************************************8 Pin Arrangements in Each Operating Mode (FP-80A) ****************************************************12 Pin Functions *******************************************************************************************************************16 Operating Modes *************************************************************************************************************23 Mode Control Register ****************************************************************************************************29 Interrupt Mask Levels ******************************************************************************************************36 Interrupt Mask Bits after an Interrupt is Accepted **********************************************************36 Initial Values of Registers ************************************************************************************************41 General Register Data Formats ****************************************************************************************42 Data Formats in Memory *************************************************************************************************43 Data Formats on the Stack ***********************************************************************************************44 Addressing Modes ***********************************************************************************************************46 Effective Address Calculation *****************************************************************************************47 Instruction Classification *************************************************************************************************50 Data Transfer Instructions ***********************************************************************************************52 Arithmetic Instructions ****************************************************************************************************53 Logic Operation Instructions *******************************************************************************************54
3-13 3-14 3-15 3-16 3-17 4-1 (a) 4-1 (b) 4-2 4-3 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 10-1 10-2
Shift Instructions **************************************************************************************************************55 Bit-Manipulation Instructions ******************************************************************************************56 Branching Instructions *****************************************************************************************************57 System Control Instructions ********************************************************************************************59 Short-Format Instructions and Equivalent General Formats *******************************************62 Exceptions and Their Priority ******************************************************************************************81 Instruction Exceptions ******************************************************************************************************81 Exception Vector Table ****************************************************************************************************84 Stack after Exception Handling Sequence ***********************************************************************94 Interrupt Controller Registers ******************************************************************************************99 Interrupts, Vectors, and Priorities **********************************************************************************102 Assignment of Interrupt Priority Registers ********************************************************************103 Number of States before Interrupt Service ********************************************************************111 Internal Control Registers of the DTC ***************************************************************************114 Data Transfer Enable Registers *************************************************************************************115 Assignment of Data Transfer Enable Registers *************************************************************117 Addresses of DTC Vectors *********************************************************************************************121 Number of States per Data Transfer ******************************************************************************123 Number of States before Interrupt Service ********************************************************************124 DTC Control Register Information Set in RAM ***********************************************************125 Register Configuration ***************************************************************************************************128 Wait Modes ********************************************************************************************************************130 External Crystal Parameters ******************************************************************************************136 Input/Output Port Summary ******************************************************************************************140 Port 1 Registers **************************************************************************************************************142 Port 1 Pin Functions in Expanded Modes **********************************************************************145 Port 1 Pin Functions in Single-Chip Modes ******************************************************************147 Port 2 Registers **************************************************************************************************************149 Port 3 Registers **************************************************************************************************************152 Port 4 Registers **************************************************************************************************************155 Port 5 Registers **************************************************************************************************************158 Status of MOS Pull-Ups for Port 5 ********************************************************************************161 Port 6 Registers **************************************************************************************************************164 Status of MOS Pull-Ups for Port 5 ********************************************************************************167 Port 7 Registers **************************************************************************************************************168 Port 7 Pin Functions *******************************************************************************************************170 Port 8 Registers **************************************************************************************************************172 Port 9 Registers **************************************************************************************************************173 Port 9 Pin Functions *******************************************************************************************************175 Input and Output Pins of Free-Running Timer Module ************************************************179 Register Configuration ***************************************************************************************************180
10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 12-1 12-2 12-3 13-1 13-2 14-1 14-2 14-3 14-3 14-3 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 15-1 15-2 15-3 15-4 16-1 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8
Free-Running Timer Interrupts **************************************************************************************195 Synchronization by Writing to FRCs ****************************************************************************196 Effect of Changing Internal Clock Sources *******************************************************************204 Input and Output Pins of 8-Bit Timer ****************************************************************************209 8-Bit Timer Registers *****************************************************************************************************209 8-Bit Timer Interrupts ****************************************************************************************************218 Priority Order of Timer Output **************************************************************************************223 Effect of Changing Internal Clock Sources *******************************************************************223 Output Pins of PWM Timer Module *****************************************************************************228 PWM Timer Registers ***************************************************************************************************229 PWM Timer Parameters for 10MHz System Clock ******************************************************232 Register Configuration ***************************************************************************************************236 Read Addresses of TCNT and TCSR ****************************************************************************240 SCI Input/Output Pins ****************************************************************************************************247 SCI Registers *****************************************************************************************************************247 Examples of BRR Settings in Asynchronous Mode (1) ************************************************255 Examples of BRR Settings in Asynchronous Mode (2) ************************************************256 Examples of BRR Settings in Asynchronous Mode (3) ************************************************256 Examples of BRR Settings in Asynchronous Mode (4) ************************************************257 Examples of BRR Settings in Synchronous Mode ********************************************************258 Communication Formats Used by SCI **************************************************************************259 SCI Clock Source Selection *******************************************************************************************259 Data Formats in Asynchronous Mode ***************************************************************************261 Receive Errors ****************************************************************************************************************264 SCI Interrupts *****************************************************************************************************************269 SSR Bit States and Data Transfer When Multiple Receive Errors Occur *********************270 A/D Input Pins ***************************************************************************************************************275 A/D Registers *****************************************************************************************************************275 Assignment of Data Registers to Analog Input Channels *********************************************276 A/D Conversion Time (Single Mode) ****************************************************************************288 RAM Control Register ***************************************************************************************************292 ROM Usage in Each MCU Mode **********************************************************************************295 Selection of PROM Mode **********************************************************************************************296 Socket Adapter ***************************************************************************************************************297 Selection of Sub-Modes in PROM Mode **********************************************************************299 DC Characteristics (When VCC = 6.0V 0.25V, VPP = 12.5V 0.3V, VSS = 0V, Ta = 25C 5C) ************301 AC Characteristics (When VCC = 6.0V 0.25V, VPP = 12.5V 0.3V, Ta = 25C 5C) ******************************301 Erasing Conditions *********************************************************************************************************304 Socket for 84-Pin LCC Package ************************************************************************************305
18-1 18-2 20-1 20-2 20-3 20-4 20-5 20-6 20-7 A-1 (a) A-1 (b) A-1 (c) A-1 (d) A-2 A-3 A-4 A-5 A-6 A-7 A-7 A-7 A-7 A-7 A-7 A-8 (a) A-8 (b) C-1 (a) C-1 (b) C-1 (c) C-1 (d) C-1 (e) C-1 (f) C-1 (g) C-2 C-3 C-4 C-5 C-6 C-7 (a) C-7 (b)
Power-Down State *********************************************************************************************************307 Software Standby Control Register *******************************************************************************309 Absolute Maximum Ratings ******************************************************************************************319 DC Characteristics *********************************************************************************************************320 Allowable Output Current Sink Values *************************************************************************321 Bus Timing ********************************************************************************************************************322 Control Signal Timing ***************************************************************************************************324 Timing Conditions of On-Chip Supporting Modules ****************************************************325 A/D Converter Characteristics ***************************************************************************************326 Machine Language Coding [General Format] ***************************************************************346 Machine Language Coding [Special Format: Short Format] *****************************************350 Machine Language Coding [Special Format: Branch Instructions] ******************************351 Machine Language Coding [Special Format: System Control Instructions] *****************352 Operation Codes in Byte 1 *********************************************************************************************353 Operation Codes in Byte 2 (Axxx) ********************************************************************************354 Operation Codes in Byte 2 (05xx, 15xx, 0Dxx, 1Dxx, Bxxx, Cxxx, Dxxx, Exxx, Fxxx) *******************************************************************************************************************355 Operation Codes in Byte 2 (04xx, 0Cxx) **********************************************************************356 Operation Codes in Bytes 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx) **************************357 Instruction Execution Cycles (1) ***********************************************************************************361 Instruction Execution Cycles (2) ************************************************************************************362 Instruction Execution Cycles (3) ************************************************************************************363 Instruction Execution Cycles (4) ************************************************************************************364 Instruction Execution Cycles (5) ************************************************************************************365 Instruction Execution Cycles (6) ************************************************************************************366 Adjusted Value (Branch Instruction) *****************************************************************************366 Adjusted Value (Other Instructions by Addressing Modes) ******************************************366 Port 1 Port Read (Pin P10) *********************************************************************************************407 Port 1 Port Read (Pin P11) *********************************************************************************************408 Port 1 Port Read (Pin P12) *********************************************************************************************408 Port 1 Port Read (Pin P13) *********************************************************************************************409 Port 1 Port Read (Pin P14) *********************************************************************************************410 Port 1 Port Read (Pins P15, P16) ************************************************************************************411 Port 1 Port Read (Pin P17) *********************************************************************************************412 Port 2 Port Read *************************************************************************************************************413 Port 3 Port Read *************************************************************************************************************414 Port 4 Port Read *************************************************************************************************************415 Port 5 Port Read *************************************************************************************************************416 Port 6 Port Read *************************************************************************************************************417 Port 7 Port Read (Pin P70) *********************************************************************************************418 Port 7 Port Read (Pins P71, P72) ************************************************************************************419
C-7 (c) C-7 (d) C-7 (e) C-9 (a) C-9 (b) C-9 (c) C-9 (d) C-9 (e) E-1 E-2
Port 7 Port Read (Pin P73) *********************************************************************************************420 Port 7 Port Read (Pins P74-P76) ************************************************************************************421 Port 7 Port Read (Pin P77) *********************************************************************************************422 Port 9 Port Read (Pins P90, P91) ************************************************************************************424 Port 9 Port Read (Pins P92-P94) ************************************************************************************425 Port 9 Port Read (Pin P95) *********************************************************************************************426 Port 9 Port Read (Pin P96) *********************************************************************************************427 Port 9 Port Read (Pin P97) *********************************************************************************************428 Port State ************************************************************************************************************************431 Pull-up MOS State *********************************************************************************************************433
Section 1 Overview
1.1 Features
The H8/532 is an original Hitachi CMOS microcomputer unit (MCU) comprising a highperformance CPU core plus a full range of supporting functions--an entire system integrated onto a single chip. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. An internal 16-bit architecture and 16-bit access to on-chip memory enhance the CPU's data-processing capability and provide the speed needed for realtime control applications. The on-chip supporting functions include RAM, ROM, timers, a serial communication interface (SCI), A/D conversion, and I/O ports. An on-chip data transfer controller (DTC) can transfer data in either direction between memory and I/O independently of the CPU. For the on-chip ROM, a choice is offered between masked ROM and programmable ROM (PROM). The PROM version can be programmed by the user with a general-purpose PROM writer. Table 1-1 lists the main features of the H8/532 chip.
1
Table 1-1 Features
Feature CPU Description General-register machine * Eight 16-bit general registers * Five 8-bit and two 16-bit control registers High speed * Maximum clock rate: 10MHz (oscillator frequency: 20MHz) Expanded operating modes supporting external memory * Minimum mode: up to 64K-byte address space * Maximum mode: up to 1M-byte address space Highly orthogonal instruction set * Addressing modes and data size can be specified independently for each instruction 1.5 Addressing modes * Register-register operations * Register-memory operations Instruction set optimized for C language * Special short formats for frequently-used instructions and addressing modes * 1K-Byte high-speed RAM on-chip * 32K-Byte programmable or masked ROM on-chip Each channel provides: * 1 free-running counter (which can count external events) * 2 output-compare registers * 1 input capture register * One 8-bit up-counter (which can count external events) * 2 time constant registers * Generates pulses with any duty ratio from 0 to 100% * Resolution: 1/250 * An overflow generates a nonmaskable interrupt * Can also be used as an interval timer
Memory 16-Bit freerunning timer (FRT) (3 channels) 8-Bit timer (1 channel) PWM timer (3 channels) Watchdog timer (WDT) (1 channel)
2
Table 1-1 Features (cont)
Description * Asynchronous or synchronous mode (selectable) * Full duplex: can send and receive simultaneously * Built-in baud rate generator * 10-Bit resolution * 8 channels, controllable in single mode or scan mode (selectable) * Sample-and-hold function I/O ports * 57 Input/output pins (six 8-bit ports, one 5-bit port, one 4-bit port) * 8 Input-only pins (one 8-bit port) * Memory-mapped I/O Interrupt * 3 external interrupt pins (NMI, IRQ0, IRQ1) controller * 19 internal interrupts (INTC) * 8 priority levels Data transfer Performs bidirectional data transfer between memory and I/O independently controller (DTC) of the CPU Wait-state Can insert wait states in access to external memory or I/O controller (WSC) Operating 5 MCU operating modes modes * Expanded minimum modes, supporting up to 64k bytes external memory with or without using on-chip ROM (Modes 1 and 2) * Expanded maximum modes, supporting up to 1M byte external memory with or without using on-chip ROM (Modes 3 and 4) * Single-chip mode (Mode 7) 3 power-down modes * Sleep mode * Software standby mode * Hardware standby mode Other features * E clock output available * Clock generator on-chip Model Name HD6475328CG HD6475328CP HD6475328F HD6435328CP HD6435328F Package Options 84-Pin windowed LCC (CG-84) 84-Pin PLCC (CP-84) 80-Pin QFP (FP-80A) 84-Pin PLCC (CP-84) 80-Pin QFP (FP-80A) ROM PROM Feature Serial communication interface (SCI) A/D converter
Mask ROM
3
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/532 chip.
P1 7 /TMO P1 6 /IRQ 1 P1 5 /IRQ 0 P1 4 /WAIT P1 3 /BREQ P1 2 /BACK P1 1 /E P1 0 /o P2 4 /WR P2 3 /RD P2 2 /DS P2 1 /R/W P2 0 /AS Port 2
Port 1
EXTAL XTAL
Clock Generator
P3 7 /D 7 P3 6 /D 6 P3 5 /D 5 P3 4 /D 4 P3 3 /D 3 P3 2 /D 2 P3 1 /D 1 P3 0 /D 0 Port 3
RES STBY MD0 MD1 MD2
Interrupt Controller Data Transfer Controller
CPU P5 7 /A15 P5 6 /A14 P5 5 /A13 P5 4 /A12 P5 3 /A11 P5 2 /A10 P5 1 /A 9 P5 0 /A 8
AVcc AVss
10 Bits A/D Converter
Watchdog Timer
Port 6 Port 7
V cc V cc V ss V ss V ss V ss * V ss V ss
Serial Communication Interface
8 Bits Timer
PWM Timer (x 3 channel)
16 Bits Free Running Timer (x 3 channel)
Port 5
NMI
Address bus
WaitState Controller
RAM 1 kByte
PROM/Mask ROM 32 kByte
Data bus (High)
Data bus (Low)
P4 7 /A 7 P4 6 /A 6 P4 5 /A 5 P4 4 /A 4 P4 3 /A 3 P4 2 /A 2 P4 1 /A 1 P4 0 /A 0
Port 4
P6 3 /A19 P6 2 /A18 P6 1 /A17 P6 0 /A16
Port 9 P9 7 /SCK P9 6 /RXD P9 5 /TXD P9 4 /PW3 P9 3 /PW2 P9 2 /PW1 P9 1 /FTOA3 P9 0 /FTOA2
Port 8 P8 7 /AN 7 P8 6 /AN 6 P8 5 /AN 5 P8 4 /AN 4 P8 3 /AN 3 P8 2 /AN 2 P8 1 /AN 1 P8 0 /AN 0
* CP-84 and CG-84 only
Figure 1-1 Block Diagram
4
P77 /FTOA1 P76 /FTOB 3 /FTCI 3 P7 5 /FTOB 2 /FTCI 2 P74 /FTOB 1 /FTCI 1 P73 /FTI 3 /TMRI P72 /FTI 2 P71 /FTI 1 P70 /TMCI
1.3 Pin Arrangements and Functions
1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the CP-84 package. Figure 1-3 shows the pin arrangement of the CG-84 package. Figure 1-4 shows the pin arrangement of the FP-80A package.
P20 /AS P17 /TMO P16 /IRQ 1 P15 /IRQ 0 P14 /WAIT P13 /BREQ P12 /BACK P11 /E P10 /o Vss XTAL EXTAL Vss P97 /SCK P96 /RXD P95 /TXD P94 /PW3 P93 /PW2 P92 /PW1 P91 /FTOA3 P90 /FTOA2
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P21 /R/W P22 /DS P23 /RD P24 /WR Vcc MD0 MD1 MD2 STBY RES NMI NC Vss P30 /D0 P31 /D1 P32 /D2 P33 /D3 P34 /D4 P35 /D5 P36 /D6 P37 /D7
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PLCC-84
64 63 62 61 60 59 58 57 56 55 54
AVcc P87 /AN7 P86 /AN6 P85 /AN5 P84 /AN4 P83 /AN3 P82 /AN2 P81 /AN1 P80 /AN0 AVss Vss P77 /FTOA1 P76 /FTOB 3 /FTCI 3 P75 /FTOB 2 /FTCI 2 P74 /FTOB 1 /FTCI 1 P73 /FTI 3 /TMRI P72 /FTI 2 P71 /FTI 1 P70 /TMCI Vcc P63 /A19
P40 /A 0 P41 /A 1 P42 /A 2 P43 /A 3 P44 /A 4 P45 /A 5 P46 /A 6 P47 /A 7 Vss Vss P50 /A 8 P51 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /A 13 P6 1 /A 14 P6 2 /A 15
1 pin
H8/532 HD6475328CP
JAPAN
Figure 1-2 Pin Arrangement (CP-84, Top View)
5
11 10 9
P20 /AS P17 /TMO P16 /IRQ 1 P15 /IRQ 0 P14 /WAIT P13 /BREQ P12 /BACK P11 /E P10 /o Vss XTAL EXTAL Vss P97 /SCK P96 /RXD P95 /TXD P94 /PW3 P93 /PW2 P92 /PW1 P91 /FTOA3 P90 /FTOA2
8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P21 /R/W P22 /DS P23 /RD P24 /WR Vcc MD0 MD1 MD2 STBY RES NMI NC Vss P30 /D0 P31 /D1 P32 /D2 P33 /D3 P34 /D4 P35 /D5 P36 /D6 P37 /D7
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
LCC-84
64 63 62 61 60 59 58 57 56 55 54
AVcc P87 /AN7 P86 /AN6 P85 /AN5 P84 /AN4 P83 /AN3 P82 /AN2 P81 /AN1 P80 /AN0 AVss Vss P77 /FTOA1 P76 /FTOB 3 /FTCI 3 P75 /FTOB 2 /FTCI 2 P74 /FTOB 1 /FTCI 1 P73 /FTI 3 /TMRI P72 /FTI 2 P71 /FTI 1 P70 /TMCI Vcc P63 /A19
P40 /A 0 P41 /A 1 P42 /A 2 P43 /A 3 P44 /A 4 P45 /A 5 P46 /A 6 P47 /A 7 Vss Vss P50 /A 8 P51 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /A 16 P6 1 /A 17 P6 2 /A 18 Index H8/532 HD6475328CG
JAPAN
Figure 1-3 Pin Arrangement (CG-84, Top View)
6
P21 /R/W P22 /DS P23 /RD P24 /WR Vcc MD0 MD1 MD2 STBY RES NMI Vss P30 /D0 P31 /D1 P32 /D2 P33 /D3 P34 /D4 P35 /D5 P36 /D6 P37 /D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P20 /AS P17 /TMO P16 /IRQ 1 P15 /IRQ 0 P14 /WAIT P13 /BREQ P12 /BACK P11 /E P10 /o Vss XTAL EXTAL P97 /SCK P96 /RXD P95 /TXD P94 /PW3 P93 /PW2 P92 /PW1 P91 /FTOA3 P90 /FTOA2 QFP-80A
50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AVcc P87 /AN7 P86 /AN6 P85 /AN5 P84 /AN4 P83 /AN3 P82 /AN2 P81 /AN1 P80 /AN0 AVss P77 /FTOA1 P76 /FTOB 3 /FTCI 3 P75 /FTOB 2 /FTCI 2 P74 /FTOB 1 /FTCI 1 P73 /FTI 3 /TMRI P72 /FTI 2 P71 /FTI 1 P70 /TMCI Vcc P63 /A19
P40 /A 0 P41 /A 1 P42 /A 2 P43 /A 3 P44 /A 4 P45 /A 5 P46 /A 6 P47 /A 7 Vss P50 /A 8 P51 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /A 16 P6 1 /A 17 P6 2 /A 18 H8/532 HD6475328F
JAPAN
1 pin
Figure 1-4 Pin Arrangement (FP-80A, Top View)
7
1.3.2 Pin Functions Pin Arrangements in Each Operating Mode: Table 1-2 lists the arrangements of the pins of the CP-84 and CG-84 packages in each operating mode. Table 1-3 lists the arrangements for the FP80A package. Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 XTAL XTAL VSS VSS P10/o P10/o P11/E P11/E P12 / BACK P12 / BACK P13 / BREQ P13 / BREQ P14 / WAIT P14 / WAIT P15 / IRQ0 P15 / IRQ0 P16 / IRQ1 P16 / IRQ1 P17 / TMO P17 / TMO AS AS R/W R/W DS DS RD RD WR WR VCC VCC MD0 MD0 MD1 MD1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Expanded Minimum Modes Mode 1 Mode 2 XTAL XTAL VSS VSS P10/o P10/o P11/E P11/E P12 / BACK P12 / BACK P13 / BREQ P13 / BREQ P14 / WAIT P14 / WAIT P15 / IRQ0 P15 / IRQ0 P16 / IRQ1 P16 / IRQ1 P17 / TMO P17 / TMO AS AS R/W R/W DS DS RD RD WR WR VCC VCC MD0 MD0 MD1 MD1
Single-Chip Mode Mode 7 XTAL VSS P10/o P11/E P12 P13 P14 P15 / IRQ0 P16 / IRQ1 P17 / TMO P20 P21 P22 P23 P24 VCC MD0 MD1
PROM Mode NC VSS NC NC NC NC NC NC NC NC NC NC NC NC NC VCC VSS VSS
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
8
Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 MD2 MD2 STBY STBY RES RES NMI NMI NC NC VSS VSS D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 VSS VSS
Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Expanded Minimum Modes Mode 1 Mode 2 MD2 MD2 STBY STBY RES RES NMI NMI NC NC VSS VSS D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 VSS VSS
Single-Chip Mode Mode 7 MD2 STBY RES NMI NC VSS P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 VSS
PROM Mode VSS VSS VPP A9 NC VSS O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 A3 A4 A5 A6 A7 VSS
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
9
Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 VSS VSS A8 P50 / A8 A9 P51 / A9 A10 P52 / A10 A11 P53 / A11 A12 P54 / A12 A13 P55 / A13 A14 P56 / A14 A15 P57 / A15 A16 P60 / A16 A17 P61 / A17 A18 P62 / A18 A19 P63 / A19 VCC VCC P70 / TMCI P70 / TMCI P71 / FTI1 P71 / FTI1 P72 / FTI2 P72 / FTI2 P73 / FTI3 / P73 / FTI3 / TMRI TMRI P74 / FTOB1 / P74 / FTOB1 / FTCI1 FTCI1 P75 / FTOB2 / P75 / FTOB2 / FTCI2 FTCI2
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
Expanded Minimum Modes Mode 1 Mode 2 VSS VSS A8 P50 / A8 A9 P51 / A9 P52 / A10 A10 A11 P53 / A11 A12 P54 / A12 A13 P55 / A13 A14 P56 / A14 A15 P57 / A15 P60 P60 P61 P61 P62 P62 P63 P63 VCC VCC P70 / TMCI P70 / TMCI P71 / FTI1 P71 / FTI1 P72 / FTI2 P72 / FTI2 P73 / FTI3 / P73 / FTI3 / TMRI TMRI P74 / FTOB1 / P74 / FTOB1 / FTCI1 FTCI1 P75 / FTOB2 / P75 / FTOB2 / FTCI2 FTCI2
Single-Chip Mode Mode 7 VSS P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 VCC P70 / TMCI P71 / FTI1 P72 / FTI2 P73 / FTI3 / TMRI P74 / FTOB1 / FTCI1 P75 / FTOB2 / FTCI2
PROM Mode VSS A8 OE A10 A11 A12 A13 A14 CE VCC VCC NC NC VCC NC NC NC NC NC NC
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
10
Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 P76 / FTOB3 / P76 / FTOB3 / FTCI3 FTCI3 P77 / FTOA1 P77 / FTOA1 VSS VSS AVSS AVSS P80 / AN0 P80 / AN0 P81 / AN1 P81 / AN1 P82 / AN2 P82 / AN2 P83 / AN3 P83 / AN3 P84 / AN4 P84 / AN4 P85 / AN5 P85 / AN5 P86 / AN6 P86 / AN6 P87 / AN7 P87 / AN7 AVCC AVCC P90 / FTOA2 P90 / FTOA2 P91 / FTOA3 P91 / FTOA3 P92 / PW1 P92 / PW1 P93 / PW2 P93 / PW2 P94 / PW3 P94 / PW3 P95/ TXD P95/ TXD P96/ RXD P96/ RXD P97/ SCK P97/ SCK VSS VSS EXTAL EXTAL
Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Expanded Minimum Modes Mode 1 Mode 2 P76 / FTOB3 / P76 / FTOB3 / FTCI3 FTCI3 P77 / FTOA1 P77 / FTOA1 VSS VSS AVSS AVSS P80 / AN0 P80 / AN0 P81 / AN1 P81 / AN1 P82 / AN2 P82 / AN2 P83 / AN3 P83 / AN3 P84 / AN4 P84 / AN4 P85 / AN5 P85 / AN5 P86 / AN6 P86 / AN6 P87 / AN7 P87 / AN7 AVCC AVCC P90 / FTOA2 P90 / FTOA2 P91 / FTOA3 P91 / FTOA3 P92 / PW1 P92 / PW1 P93 / PW2 P93 / PW2 P94 / PW3 P94 / PW3 P95/ TXD P95 / TXD P96 / RXD P96/ RXD P97 / SCK P97/ SCK VSS VSS EXTAL EXTAL
Single-Chip Mode Mode 7 P76/ FTOB3 / FTCI3 P77 / FTOA1 VSS AVSS P80 / AN0 P81 / AN1 P82 / AN2 P83 / AN3 P84 / AN4 P85 / AN5 P86 / AN6 P87 / AN7 AVCC P90 / FTOA2 P91 / FTOA3 P92 / PW1 P93 / PW2 P94 / PW3 P95/ TXD P96/ RXD P97/ SCK VSS EXTAL
PROM Mode NC NC VSS VSS NC NC NC NC NC NC NC NC VCC NC NC NC NC NC NC NC NC VSS NC
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
11
Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 R/W R/W DS DS RD RD WR WR VCC VCC MD0 MD0 MD1 MD1 MD2 MD2 STBY STBY RES RES NMI NMI VSS VSS D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 A0 A0
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Expanded Minimum Modes Mode 1 Mode 2 R/W R/W DS DS RD RD WR WR VCC VCC MD0 MD0 MD1 MD1 MD2 MD2 STBY STBY RES RES NMI NMI VSS VSS D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 A0 A0
Single-Chip Mode Mode 7 P21 P22 P23 P24 VCC MD0 MD1 MD2 STBY RES NMI VSS P30 P31 P32 P33 P34 P35 P36 P37 P40
PROM Mode NC NC NC NC VCC VSS VSS VSS VSS VPP A9 VSS O0 O1 O2 O3 O4 O5 O6 O7 A0
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
12
Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 VSS VSS A8 P50/ A8 A9 P51/ A9 A10 P52/ A10 A11 P53 / A11 A12 P54 / A12 A13 P55 / A13 A14 P56 / A14 A15 P57 / A15 A16 P60 / A16 A17 P61 / A17 A18 P62 / A18 A19 P63 / A19 VCC VCC
Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Expanded Minimum Modes Mode 1 Mode 2 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 VSS VSS A8 P50 / A8 A9 P51 / A9 A10 P52 / A10 A11 P53 / A11 A12 P54 / A12 A13 P55 / A13 A14 P56 / A14 A15 P57 / A15 P60 P60 P61 P61 P62 P62 P63 P63 VCC VCC
Single-Chip Mode Mode 7 P41 P42 P43 P44 P45 P46 P47 VSS P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 VCC
PROM Mode A1 A2 A3 A4 A5 A6 A7 VSS A8 OE A10 A11 A12 A13 A14 CE VCC VCC NC NC VCC
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
13
Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 P70/ TMCI P70/ TMCI P71/ FTI1 P71/ FTI1 P72 / FTI2 P72 / FTI2 P73 / FTI3 / P73 / FTI3 / TMRI TMRI P74 / FTOB1 / P74/ FTOB1 / FTCI1 FTCI1 P75 / FTOB2 / P75 / FTOB2 / FTCI2 FTCI2 P76 / FTOB3 / P76 / FTOB3 / FTCI3 FTCI3 P77 / FTOA1 P77 / FTOA1 AVSS AVSS P80 / AN0 P80 / AN0 P81 / AN1 P81 / AN1 P82 / AN2 P82 / AN2 P83 / AN3 P83 / AN3 P84 / AN4 P84 / AN4 P85 / AN5 P85 / AN5 P86 / AN6 P86 / AN6 P87 / AN7 P87 / AN7
Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
Expanded Minimum Modes Mode 1 Mode 2 P70 / TMCI P70/ TMCI P71/ FTI1 P71 / FTI1 P72 / FTI2 P72 / FTI2 P73 / FTI3 / P73 / FTI3 / TMRI TMRI P74 / FTOB1 / P74 / FTOB1 / FTCI1 FTCI1 P75 / FTOB2 / P75 / FTOB2 / FTCI2 FTCI2 P76 / FTOB3 / P76 / FTOB3 / FTCI3 FTCI3 P77 / FTOA1 P77 / FTOA1 AVSS AVSS P80 / AN0 P80 / AN0 P81 / AN1 P81 / AN1 P82 / AN2 P82 / AN2 P83 / AN3 P83 / AN3 P84 / AN4 P84 / AN4 P85 / AN5 P85 / AN5 P86 / AN6 P86 / AN6 P87 / AN7 P87 / AN7
Single-Chip Mode Mode 7 P70/ TMCI P71/ FTI1 P72 / FTI2 P73 / FTI3 / TMRI P74 / FTOB1 / FTCI1 P75 / FTOB2 / FTCI2 P76 / FTOB3 / FTCI3 P77 / FTOA1 AVSS P80 / AN0 P81 / AN1 P82 / AN2 P83 / AN3 P84 / AN4 P85 / AN5 P86 / AN6 P87 / AN7
PROM Mode NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
14
Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont)
Pin Name Expanded Maximum Modes Mode 3 Mode 4 AVCC AVCC P90 / FTOA2 P90 / FTOA2 P91 / FTOA3 P91 / FTOA3 P92 / PW1 P92 / PW1 P93 / PW2 P93 / PW2 P94 / PW3 P94 / PW3 P95 / TXD P95 / TXD P96 / RXD P96 / RXD P97 / SCK P97 / SCK EXTAL EXTAL XTAL XTAL VSS VSS P10 / o P10 / o P11 / E P11 / E P12 / BACK P12 / BACK P13 / BREQ P13 / BREQ P14 / WAIT P14 / WAIT P15 / IRQ0 P15 / IRQ0 P16 / IRQ1 P16 / IRQ1 P17 / TMO P17 / TMO AS AS
Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Expanded Minimum Modes Mode 1 Mode 2 AVCC AVCC P90 / FTOA2 P90 / FTOA2 P91 / FTOA3 P91 / FTOA3 P92 / PW1 P92 / PW1 P93 / PW2 P93 / PW2 P94 / PW3 P94 / PW3 P95 / TXD P95 / TXD P96 / RXD P96 / RXD P97 / SCK P97 / SCK EXTAL EXTAL XTAL XTAL VSS VSS P10 / o P10 / o P11 / E P11 / E P12 / BACK P12 / BACK P13 / BREQ P13 / BREQ P14 / WAIT P14 / WAIT P15 / IRQ0 P15 / IRQ0 P16 / IRQ1 P16 / IRQ1 P17 / TMO P17 / TMO AS AS
Single-Chip Mode Mode 7 AVCC P90 / FTOA2 P91 / FTOA3 P92 / PW1 P93 / PW2 P94 / PW3 P95 / TXD P96 / RXD P97 / SCK EXTAL XTAL VSS P10 / o P11 / E P12 P13 P14 P15 / IRQ0 P16 / IRQ1 P17 / TMO P20
PROM Mode VCC NC NC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC NC
Notes: 1. For the PROM mode, see section 17, "ROM." 2. Pins marked NC should be left unconnected.
15
Pin Functions: Table 1-4 gives a concise description of the function of each pin. Table 1-4 Pin Functions
Pin No. CP-84, CG-84 FP-80A 16, 55 5, 42
Type Power
Symbol VCC
VSS
2, 24 41, 42 64, 83 1
12, 29 71
Clock
XTAL
70
EXTAL
84
69
o E System control BACK
3 4 5
72 73 74
I/O Name and Function I Power: Connected to the power supply (+5V). Connect both VCC pins to the system power supply (+5V). The chip will not operate if either pin is left unconnected. I Ground: Connected to ground (0V). Connect all VSS pins to the system power supply (0V). The chip will not operate if any VSS pin is left unconnected. I Crystal: Connected to a crystal oscillator. The crystal frequency should be double the desired o clock frequency. If an external clock is input at the EXTAL pin, leave the XTAL pin unconnected. I External Crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be double the desired o clock frequency. See section 8.2, "Oscillator Circuit" for examples of connections to a crystal and external clock. O System Clock: Supplies the o clock to peripheral devices. O Enable Clock: Supplies an E clock to E clock based peripheral devices. O Bus Request Acknowledge: Indicates that the bus right has been granted to an external device. Notifies an external device that issued a BREQ signal that it now has control of the bus.
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Table 1-4 Pin Functions (cont)
Pin No. CP-84, CG-84 FP-80A 6 75 20 9
Type System control
Symbol BREQ STBY
RES Address A19 - A0 bus Data bus D7 - D0 Bus WAIT control AS R/W
21 54 - 43 40 - 33 32 - 25 7 11 12
10 41 - 30 28 - 21 20 - 13 76 80 1
I/O Name and Function I Bus Request: Sent by an external device to the H8/532 chip to request the bus right. I Standby: A transition to the hardware standby mode (a power-down state) occurs when a Low input is received at the STBY pin. I Reset: A Low input causes the H8/532 chip to reset. O Address Bus: Address output pins. I/O Data Bus: 8-Bit bidirectional data bus. I Wait: Requests the CPU to insert one or more Tw states when accessing an off-chip address. O Address Strobe: Goes Low to indicate that there is a valid address on the address bus. O Read/Write: Indicates whether the CPU is reading or writing data on the bus. * High--Read * Low--Write O Data Strobe: Goes Low to indicate the presence of valid data on the data bus. O Read: Goes Low to indicate that the CPU is reading an external address. O Write: Goes Low to indicate that the CPU is writing to an external address.
DS RD WR
13 14 15
2 3 4
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Table 1-4 Pin Functions (cont)
Type Interrupt
Pin No. CP-84, Symbol CG-84 FP-80A NMI 22 11
IRQ0 IRQ1 Operating MD2 mode MD1 control MD0
8 9 19 18 17
77 78 8 7 6
I/O Name and Function I NonMaskable Interrupt: Highest-signals priority interrupt request. The port 1 control register (P1CR) determines whether the interrupt is requested on the rising or falling edge of the NMI input. I Interrupt Request 0 and 1: Maskable interrupt request pins. I Mode: Input pins for setting the MCU operating mode according to the table below. MD2 MD1 MD0 Mode Description 0 0 0 Mode 0 -- 0 0 1 Mode 1 Expanded minimum mode (ROM disabled) 0 1 0 Mode 2 Expanded minimum mode (ROM enabled) 0 1 1 Mode 3 Expanded maximum mode (ROM disabled) 1 0 0 Mode 4 Expanded maximum mode (ROM enabled) 1 0 1 Mode 5 -- 1 1 0 Mode 6 -- 1 1 1 Mode 7 Single-chip mode The inputs at these pins are latched in mode select bits 2 to 0 (MDS2 - MDS0) of the mode control register (MDCR) on the rising edge of the RES signal.
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Table 1-4 Pin Functions (cont)
Type 16-Bit freerunning timer (FRT)
Symbol FTOA1 FTOA2 FTOA3 FTOB1 FTOB2 FTOB3 FTCI1 FTCI2 FTCI3 FTI1 FTI2 FTI3 TMO TMCI TMRI
Pin No. CP-84, CG-84 FP-80A 63 50 75 61 76 62 60 47 61 48 62 49 60 47 61 48 62 49 57 58 59 10 56 59 77 78 79 44 45 46 79 43 46 63 64 65
I/O O
O
I
I
8-Bit timer
O I I O
PWM timer
PW1 PW2 PW3
Name and Function FRT Output Compare A (channels 1, 2, and 3): Output pins for the output compare A function of the free-running timer channels 1, 2, and 3. FRT Output Compare B (channels 1, 2, and 3): Output pins for the output compare B function of the free-running timer channels 1, 2, and 3. FRT Counter Clock Input (channels 1, 2, and 3): External clock input pins for the free-running counters (FRCs) of free-running timer channels 1, 2, and 3. FRT Input Capture (channels 1, 2, and 3): Input capture pins for free-running timer channels 1, 2, and 3. 8-bit Timer Output: Compare-match output pin for the 8-bit timer. 8-bit Timer Clock Input: External clock input pin for the 8-bit timer counter. 8-bit Timer Counter Reset Input: A high input at this pin resets the 8-bit timer counter. PWM Timer Output (channels 1, 2, and 3): Pulse-width modulation timer output pulses.
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Table 1-4 Pin Functions (cont)
Pin No. CP-84, CG-84 FP-80A I/O Name and Function 80 66 O Transmit Data: Data output pins for the serial communication interface. 81 82 67 68 59 - 52 60 51 79 - 72 Receive Data: Data input pins for the serial communication interface. I/O Serial Clock: Input/output pin for the serial interface clock. I Analog Input: Analog signal input pins. I I I/O Analog Reference Voltage: Reference voltage and power supply pin for the A/D converter. Analog Ground: Ground pin for the A/D converter. Port 1: An 8-bit input/output port. The direction of each bit is determined by the port 1 data direction register (P1DDR). Port 2: A 5-bit input/output port. The direction of each bit is determined by the port 2 data direction register (P2DDR). Port 3: An 8-bit input/output port. The direction of each bit is determined by the port 3 data direction register (P3DDR). Port 4: An 8-bit input/output port. The direction of each bit is determined by the port 4 data direction register (P4DDR). These pins can drive LED indicators. I
Type Symbol Serial com- TXD munication interface signals RXD SCK A/D converter
AN7 - AN0 73 - 66 AVCC* AVSS* 74 65
Parallel I/O
P17 - P10 10 - 3
P24 - P20 15 - 11
4 - 1, 80 20 - 13
I/O
P37 - P30 32 - 25
I/O
P47 - P40 40 - 33
28 - 21
I/O
* When A/D converter is not used, AVCC should be connected to VCC, and AVSS should be connected to GND.
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Table 1-4 Pin Functions (cont)
Pin No. CP-84, CG-84 FP-80A I/O Name and Function 50 - 43 37 - 30 I/O Port 5: An 8-bit input/output port. The direction of each bit is determined by the port 5 data direction register (P5DDR). These pins have built-in MOS input pull-ups. 54 - 51 41 - 38 I/O Port 6: A 4-bit input/output port. The direction of each bit is determined by the port 6 data direction register (P6DDR). These pins have built-in MOS input pull-ups. 63 - 56 50 - 43 I/O Port 7: An 8-bit input/output port. The direction of each bit is determined by the port 7 data direction register (P7DDR). These pins have Schmitt inputs. 73 - 66 59 - 52 I Port 8: An 8-bit input port 82 - 75 68 - 61 I/O Port 9: An 8-bit input/output port. The direction of each bit is determined by the port 9 data direction register (P9DDR).
Type Parallel I/O
Symbol P57 - P50
P63 - P60
P77 - P70
P87 - P80 P97 - P90
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Section 2 MCU Operating Modes and Address Space
2.1 Overview
The H8/532 microcomputer unit (MCU) operates in five modes numbered 1, 2, 3, 4, and 7. The mode is selected by the inputs at the mode pins (MD2 to MD0) at the instant when the chip comes out of a reset. As indicated in table 2-1, the MCU mode determines the size of the address space, the usage of on-chip ROM, and the operating mode of the CPU. The MCU mode also affects the functions of I/O pins. Table 2-1 Operating Modes
MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 MCU Mode -- Mode 1 Mode 2 Mode 3 Mode 4 -- -- Mode 7 Address Space -- Expanded minimum Expanded minimum Expanded maximum Expanded maximum -- -- Single-chip only On-Chip ROM -- Disabled Enabled Disabled Enabled -- -- Enabled CPU Mode -- Minimum mode Minimum mode Maximum mode Maximum mode -- -- Minimum mode
Notation: 0: Low level 1: High level --: Cannot be used
Modes 1 to 4 are referred to as "expanded" because they permit access to off-chip memory and peripheral addresses. The expanded minimum modes (modes 1 and 2) support a maximum address space of 64K bytes. The expanded maximum modes (modes 3 and 4) support a maximum address space of 1M byte. Interrupt service is slightly slower in the expanded maximum modes than in the other modes because the CPU has to save its code page register. The H8/532 cannot be set to modes 0, 5, and 6. The mode pins should never be set to these values.
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2.2 Mode Descriptions
The five MCU modes are described below. For further information on the I/O pin functions in each mode, see section 9, "I/O Ports." Mode 1 (Expanded Minimum Mode): Mode 1 supports a maximum 64K-byte address space which does not include any on-chip ROM. Ports 1 to 5 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus: Port 3 Address bus: Ports 4 and 5 * The functions of individual pins of port 1 are software-selectable. Mode 2 (Expanded Minimum Mode): Mode 2 supports a maximum 64K-byte address space of which the first 32K bytes are in on-chip ROM. Ports 1 to 5 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus: Port 3 Address bus: Ports 4 and 5* * The functions of individual pins in ports 1 and 5 are software-selectable. Note: In mode 2, port 5 is initially a general-purpose input port. Software must change it to output before using it for the address bus. See section 9.6, "Port 5" for details. The following instruction makes all pins of port 5 into output pins: MOV.B #H'FF, @H'FF88*
* H'xx or H'xxxx express the hexadecimal number. Mode 3 (Expanded Maximum Mode): Mode 3 supports a maximum 1M-byte address space which does not include any on-chip ROM. Ports 1 to 6 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus: Port 3 Address bus: Ports 4, 5, and 6 * The functions of individual pins of port 1 are software-selectable.
24
Mode 4 (Expanded Maximum Mode): Mode 4 supports a maximum 1M-byte address space of which the first 32K bytes are in on-chip ROM. Ports 1 to 6 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus: Port 3 Address bus: Ports 4, 5*, and 6* * The functions of individual pins in ports 1, 5, and 6 are software-selectable. Note: In mode 4, ports 5 and 6 are initially general-purpose input ports. Software must change them to output before using them for the address bus. See section 9.6, "Port 5" and 10.7, "Port 6" for details. The following instruction sets all pins of ports 5 and 6 to output: MOV.W #H'FFFF, @H'FF88 Mode 7 (Single-Chip Mode): In this mode all memory is on-chip, in 32K bytes of ROM and 1K byte of RAM. It is not possible to access off-chip addresses. The single-chip mode provides the maximum number of ports. All the pins associated with the address and data buses in the expanded modes are available as general-purpose input/output ports in the single-chip mode.
2.3 Address Space Map
2.3.1 Page Segmentation The H8/532's address space is segmented into 64K-byte pages. In the single-chip mode and expanded minimum modes there is just one page: page 0. In the expanded maximum modes there can be up to 16 pages. Figure 2-1 shows the address space in each mode and indicates which parts are on- and off-chip.
25
Expanded minimum modes Address H'00000 Mode 1 Mode 2
Expanded maximum modes Mode 3 Mode 4
Single-chip mode Mode 7
Page 0
H'0FFFF H'10000
Page 1
H'1FFFF
H'F0000
Page 15
H'FFFFF On-chip On- or off-chip (selectable) Off-chip
Figure 2-1 Address Space in Each Mode
26
2.3.2 Page 0 Address Allocations The high and low address areas in page 0 are reserved for registers and vector tables. Vector Tables: The low address area contains the exception vector table and DTC vector table. The CPU accesses the exception vector table to obtain the addresses of user-coded exceptionhandling routines. The DTC vector table contains pointers to tables of register information used by the on-chip chip data transfer controller. The size of these tables depends on the CPU operating mode. Details are given in section 4.1.3, "Exception Factors and Vector Table," section 5.2.3, "Interrupt Vector Table," and section 6.3.2, "DTC Vector Table." In modes 2 and 4 the vector tables are located in on-chip ROM. In modes 1, 3, and 7 the vector tables are in external memory. Register Field: The highest 128 addresses in page 0 (addresses H'FF80 to H'FFFF) belong to control, status, and data registers used by the I/O ports and on-chip supporting modules. Program code cannot be located at these addresses. The CPU accesses addresses in this register field like other addresses in the address space. By reading and writing at these addresses the CPU controls the on-chip supporting modules and communicates via the I/O ports. A complete map of the register field is given in appendix B. On-Chip RAM: One of the control registers in the register field is a RAM control register (RAMCR) containing a RAM enable bit (RAME) that enables or disables the 1-kbyte on-chip RAM. When this bit is set to "1" (its default value), addresses H'FFB0 to H'FF7F are located onchip. When this bit is cleared to "0," these addresses are located in external memory and the onchip RAM is not used. See section 16, "RAM" for further information. The RAME bit is bit 7 at address H'FFF9. Coding Example: To enable on-chip RAM: BSET.B #7, @H'FFF9 To disable on-chip RAM: BCLR.B #7, @H'FFF9 Note: If on-chip RAM is disabled in the single-chip mode, access to addresses H'FFB0 to H'FF7F causes an address error.
27
Figure 2-2 is a map of page 0 of the address space.
H'0000 Exception vector table DTC vector table
On-chip ROM (modes 2, 4, and 7) or external memory (modes 1 and 3)
H'7FFF H'8000
H'FB80 On-chip RAM (when enabled) H'FF80 On-chip register field H'FFFF
Figure 2-2 Map of Page 0
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2.4 Mode Control Register (MDCR)
Another control register in the register field in page 0 is the mode control register (MDCR). The inputs at the mode pins are latched in this register on the rising edge of the signal. The mode control register can be read by the CPU, but not written. Table 3-2 lists the attributes of this register. Table 2-2 Mode Control Register
Name Mode control register Abbreviation MDCR Read/Write Read only Address H'FFFA
The bit configuration of this register is shown below.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 * R 1 MDS1 * R 0 MDS0 * R
* Initialized according to MD2 to MD0. Bits 7 and 6--Reserved: These bits cannot be modified and are always read as "1." Bits 5 to 3--Reserved: These bits cannot be modified and are always read as "0." Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the values of the mode pins (MD2 to MD0) latched on the rising edge of the signal. MDS2 corresponds to MD2, MDS1 to MD1, and MDS0 to MD0. These bits can be read but not written. Coding Example: To test whether the MCU is operating in mode 1: CMP:G.B #H'C1, @H'FFFA The comparison is with H'C1 instead of H'01 because bits 7 and 6 are always read as "1."
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Section 3 CPU
3.1 Overview
The H8/532 chip has the H8/500 Family CPU: a high-speed central processing unit designed for realtime control of a wide range of medium-scale office and industrial equipment. Its Hitachioriginal architecture features eight 16-bit general registers, internal 16-bit data paths, and an optimized instruction set. Section 3 summarizes the CPU architecture and instruction set. 3.1.1 Features The main features of the H8/500 CPU are listed below. * General-register machine -- Eight 16-bit general registers -- Seven control registers (two 16-bit registers, five 8-bit registers) * High speed: maximum 10MHz At 10MHz a register-register add operation takes only 200ns. * Address space managed in 64k-byte pages, expandable to 1M byte* Page registers make four pages available simultaneously: a code page, stack page, data page, and extended page. * Two CPU operating modes: -- Minimum mode: Maximum 64k-byte address space -- Maximum mode: Maximum 1M-byte address space* * Highly orthogonal instruction set Addressing modes and data sizes can be specified independently within each instruction. * 1.5 Addressing modes Register-register and register-memory operations are supported. * Optimized for efficient programming in C language In addition to the general registers and orthogonal instruction set, the CPU has special short formats for frequently-used instructions and addressing modes. * The CPU architecture supports up to 16M bytes of external memory, but the H8/532 chip has only enough address pins to address 1M byte.
31
3.1.2 Address Space The address space size depends on the operating mode. The H8/532 MCU has five operating modes, which are selected by the input to the mode pins (MD2 to MD0) when the chip comes out of a reset. The CPU, however, has only two operating modes. The MCU operating mode determines the CPU operating mode, which in turn determines the maximum address space size as indicated in figure 3-1.
Minimum mode CPU operating mode Maximum mode
Maximum address space: 64 k bytes Hightest address: H'FFFF Maximum address space: 1 M byte Hightest address: H'FFFFF
Figure 3-1 CPU Operating Modes
32
3.1.3 Register Configuration Figure 3-2 shows the register structure of the CPU. There are two groups of registers: the general registers (Rn) and control registers (CR).
General registers (Rn) 15 R0 R1 R2 R3 R4 R5 R6 R7 (FP) (SP)
0
FP: Frame Pointer SP: Stack Pointer
Control registers (CR) 15 PC 0 PC: Program Counter
SR
CCR 15
T
87
0
I2 I1 I0
N ZV C
CP DP EP TP BR
SR: Status Register CCR: Condition Code Register CP: Code Page register DP: Data Page register EP: Extended Page register TP: sTack Page register BR: Base Register
Figure 3-2 Registers in the CPU
33
3.2 CPU Register Descriptions
3.2.1 General Registers All eight of the 16-bit general registers are functionally alike; there is no distinction between data registers and address registers. When these registers are accessed as data registers, either byte or word size can be selected. R6 and R7, in addition to functioning as general registers, have special assignments. R7 is the stack pointer, used implicitly in exception handling and subroutine calls. It can be designated by the name SP, which is synonymous with R7. As indicated in figure 3-3, it points to the top of the stack. It is also used implicitly by the LDM and STM instructions, which load and store multiple registers from and to the stack and pre-decrement or post-increment R7 accordingly. R6 functions as a frame pointer (FP). The LINK and UNLK use R6 implicitly to reserve or release a stack frame.
Unused area SP Stack area
Figure 3-3 Stack Pointer
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3.2.2 Control Registers The CPU control registers (CR) include a 16-bit program counter (PC), a 16-bit status register (SR), four 8-bit page registers, and one 8-bit base register (BR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Status Register (SR): This 16-bit register contains internal status information. The lower half of the status register is referred to as the condition code register (CCR): it can be accessed as a separate condition code byte. CCR Bit 15 T 14 -- 13 -- 12 -- 11 -- 10 I2 9 I1 8 I0 7 -- 6 -- 5 -- 4 -- 3 N 2 Z 1 V 0 C
Bit 15--Trace (T): When this bit is set to "1," the CPU operates in trace mode and generates a trace exception after every instruction. See section 4.4, "Trace" for a description of the trace exception-handling sequence. When the value of this bit is "0," instructions are executed in normal continuous sequence. This bit is cleared to "0" at a reset. Bits 14 to 11--Reserved: These bits cannot be modified and are always read as "0." Bits 10 to 8--Interrupt Mask (I2, I1, I0): These bits indicate the interrupt request mask level (0 to 7). As shown in table 3-1, an interrupt request is not accepted unless it has a higher level than the value of the mask. A nonmaskable interrupt (NMI), which has level 8, is accepted at any mask level. After an interrupt is accepted, I2, I1, and I0 are changed to the level of the interrupt. Table 3-2 indicates the values of the I bits after an interrupt is accepted. A reset sets all three of bits (I2, I1, and I0) to "1," masking all interrupts except NMI.
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Table 3-1 Interrupt Mask Levels
Mask Level 7 6 5 4 3 2 1 0 Mask Bits I2 I1 I0 111 110 101 100 011 010 001 000
Priority High
Low
Interrupts Accepted NMI Level 7 and NMI Levels 6 to 7 and NMI Levels 5 to 7 and NMI Levels 4 to 7 and NMI Levels 3 to 7 and NMI Levels 2 to 7 and NMI Levels 1 to 7 and NMI
Table 3-2 Interrupt Mask Bits after an Interrupt is Accepted
Level of Interrupt Accepted NMI (8) 7 6 5 4 3 2 1 I2 1 1 1 1 1 0 0 0 I1 1 1 1 0 0 1 1 0 I0 1 1 0 1 0 1 0 1
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Bits 7 to 4--Reserved: These bits cannot be modified and are always read as "0." Bit 3--Negative (N): This bit indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero (Z): This bit is set to "1" to indicate a zero result and cleared to "0" to indicate a nonzero result. Bit 1--Overflow (V): This bit is set to "1" when an arithmetic overflow occurs, and cleared to "0" at other times. Bit 0--Carry (C): This bit is set to "1" when a carry or borrow occurs at the most significant bit, and is cleared to "0" (or left unchanged) at other times. The specific changes that occur in the condition code bits when each instruction is executed are listed in appendix A.1 "Instruction Tables." See the H8/500 Series Programming Manual for further details. Page Registers: The code page register (CP), data page register (DP), extended page register (EP), and stack page register (TP) are 8-bit registers that are used only in the maximum mode. No use of their contents is made in the minimum mode. In the maximum mode, the page registers combine with the program counter and general registers to generate 24-bit effective addresses as shown in figure 3-4, thereby expanding the program area, data area, and stack area.
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Page register 8 Bits
PC or general register 16 Bits
CP
PC
R0 R1 DP R2 R3 @ aa : 16
R4 EP R5
R6 TP R7
24 Bits (effective address) Figure 3-4 Combinations of Page Registers with Other Registers Code Page Register (CP): The code page register and the program counter combine to generate a 24-bit program code address. In the maximum mode, the code page register is initialized at a reset to a value loaded from the vector table, and both the code page register and program counter
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are saved and restored in exception handling. Data Page Register (DP): The data page register combines with general registers R0 to R3 to generate a 24-bit effective address. The data page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R0 to R3, and in the 16-bit absolute addressing mode (@aa:16). The data page register is rewritten by the LDC instruction. Extended Page Register (EP): The extended page register combines with general register R4 or R5 to generate a 24-bit operand address. The extended page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R4 or R5. The extended page can be used as an additional data page. Stack Page Register (TP): The stack page register combines with R6 (FP) or R7 (SP) to generate a 24-bit stack address. The stack page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R6 or R7, in exception handling, and subroutine calls. Base Register (BR): This 8-bit register stores the base address used in the short absolute addressing mode (@aa:8). In this addressing mode a 16-bit effective address in page 0 is generated by using the contents of the base register as the upper 8 bits and an address given in the instruction code as the lower 8 bits. See figure 3-5. In the short absolute addressing mode the address is always located in page 0.
8 Bits
8 Bits
BR
@ aa : 8
16 Bits (effective address) Figure 3-5 Short Absolute Addressing Mode and Base Register
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3.2.3 Initial Register Values When the CPU is reset, its internal registers are initialized as shown in table 3-3. Note that the stack pointer (R7) and base register (BR) are not initialized to fixed values. Also, of the page registers used in maximum mode, only the code page register (CP) is initialized; the other three page registers come out of the reset state with undetermined values. Accordingly, in the minimum mode the first instruction executed after a reset should initialize the stack pointer. The base register must also be initialized before the short absolute addressing mode (@aa:8) is used. In the maximum mode, the first instruction executed after a reset should initialize the stack page register (TP) and the next instruction should initialize the stack pointer. Later instructions should initialize the base register and the other page registers as necessary.
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Table 3-3 Initial Values of Registers
Initial Value Maximum Mode Undetermined
Register General registers 15 R7 - R0 Control registers 15 PC SR CCR
Minimum Mode 0 Undetermined
0
Loaded from vector table
Loaded from vector table
15 87 0 T- - - - I2I1I0 - - - - NZVC 7 0 CP 7 0 DP 7 0 EP 7 0 TP 7 0 BR
H'070x (x: undetermined) Undetermined Undetermined Undetermined Undetermined Undetermined
H'070x (x: undetermined) Loaded from vector table Undetermined Undetermined Undetermined Undetermined
3.3 Data Formats
The H8/500 can process 1-bit data, 4-bit BCD data, 8-bit (byte) data, 16-bit (word) data, and 32bit (longword) data. * Bit manipulation instructions operate on 1-bit data. * Decimal arithmetic instructions operate on 4-bit BCD data. * Almost all instructions operate on byte and word data. * Multiply and divide instructions operate on longword data. 3.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in table 3-4.
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Bit data locations are specified by bit number. Bit 15 is the most significant bit. Bit 0 is the least significant bit. BCD and byte data are stored in the lower 8 bits of a general register. Word data use all 16 bits of a general register. Longword data use two general registers: the upper 16 bits are stored in Rn (n must be an even number); the lower 16 bits are stored in Rn+1. Operations performed on BCD data or byte data do not affect the upper 8 bits of the register. Table 3-4 General Register Data Formats
Data Type 1-Bit Rn BCD
15 8 Don't-care 7 Upper digit 4 3 Lower digit 0
Register No.
Data Structure
15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0
Rn Byte
15
8 Don't-care
7 MSB LSB
0
Rn Word
15
0 LSB
Rn Longword Rn* Rn+1*
MSB
31 MSB Upper 16 bits Lower 16 bits 15 LSB
16
0
* For longword data n must be even (0, 2, 4, or 6).
3.3.2 Data Formats in Memory Table 3-5 indicates the data formats in memory. Instructions that access bit data in memory have byte or word operands. The instruction specifies a bit number to indicate a specific bit in the operand. Access to word data in memory must always begin at an even address. Access to word data starting at an odd address causes an address error. The upper 8 bits of word data are stored in address n (where n is an even number); the lower 8 bits are stored in address n+1.
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Table 3-5 Data Formats in Memory
Data Type 1-Bit (in byte operand data) Data Format
7 Address n 1-Bit (in word operand data) Even address Odd address Byte 15 7 14 6 13 5 12 4 11 3 10 2 9 1 7 6 5 4 3 2 1
0 0
8 0
Address n Word
MSB
LSB
Even address Odd address
MSB
Upper 8 bits Lower 8 bits LSB
When the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size. Similarly, when the stack is accessed by an instruction using the pre-decrement or postincrement register indirect addressing mode specifying R7 (@-R7 or @R7+), which is the stack pointer, word access is performed regardless of the operand size specified in the instruction. An address error will therefore occur if the stack pointer indicates an odd address. Programs should be coded so that the stack pointer always indicates an even address. Table 3-6 shows the data formats on the stack.
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Table 3-6 Data Formats on the Stack
Data Type Byte data on stack Data Format
Even address Odd address Word data on stack Even address Odd address MSB MSB
Don't-care LSB
Upper 8 bits Lower 8 bits LSB
3.4 Instructions
3.4.1 Basic Instruction Formats There are two basic CPU instruction formats: the general format and the special format. General format: This format consists of an effective address (EA) field, an effective address extension field, and an operation code (OP) field. The effective address is placed before the operation code because this results in faster execution of the instruction.
Effective address field Effective address extension Operation code
* Effective address field:
One byte containing information used to calculate the effective address of an operand.
* Effective address extension: Zero to two bytes containing a displacement value, immediate data, or an absolute address. The size of the effective address extension is specified in the effective address field. * Operation code: Defines the operation to be carried out on the operand located at the address calculated from the effective address information. Some instructions (DADD, DSUB, MOVFPE, MOVTPE) have an extended format in which the operand code is preceded by a one-byte prefix code.
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* (Example of prefix code in DADD instruction)
Effective address Prefix code Operation code
10100rrr
00000000
10100rrr
Special Format: In this format the operation code comes first, followed by the effective address field and effective address extension. This format is used in branching instructions, system control instructions, and other instructions that can be executed faster if the operation is specified before the operand.
Operation code
Effective address field
Effective address extension
* Operation code: One or two bytes defining the operation to be performed by the instruction. * Effective address field and effective address extension: Zero to three bytes containing information used to calculate an effective address. 3.4.2 Addressing Modes The CPU supports 7 addressing modes: (1) register direct; (2) register indirect; (3) register indirect with displacement; (4) register indirect with pre-decrement or post-increment; (5) immediate; (6) absolute; and (7) PC-relative. Due to the highly orthogonal nature of the instruction set, most instructions having operands can use any applicable addressing mode from (1) through (6). The PC-relative mode (7) is used by branching instructions. In most instructions, the addressing mode is specified in the effective address field. The effectiveaddress extension, if present, contains a displacement, immediate data, or an absolute address. Table 3-7 indicates how the addressing mode is specified in the effective address field.
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Table 3-7 Addressing Modes
No. 1 Addressing Mode Register direct Mnemonic Rn EA Field 1 0 1 0 Sz r r r
*1 *2
EA Extension None
2 3
Register indirect Register indirect with displacement
@Rn @(d:8,Rn) @(d:16,Rn)
1 1 0 1 Sz r r r 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r
None Displacement (1 byte) Displacement (2 bytes)
4
Register indirect with pre-decrement Register indirect with post-increment Immediate
@-Rn @Rn+
None 1 1 0 0 Sz r r r
5
#xx:8 #xx:16
00000100 00001100 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 No EA field. Addressing mode is specified in the operation code.
Immediate data (1 byte) Immediate data (2 bytes) 1-Byte absolute address (offset from BR) 2-Byte absolute address 1- or 2-byte displacement
6
Absolute *3
@aa:8 @aa:16
7
PC-relative
disp
Notes: * 1 Sz: Specifies the operand size. When Sz = 0: byte operand When Sz = 1: word operand * 2 rrr: Register number field, specifying a general register number. 0 0 0 -- R0 0 0 1 -- R1 0 1 0 -- R2 0 1 1 -- R3 1 0 0 -- R4 1 0 1 -- R5 1 1 0 -- R6 1 1 1 -- R7 * 3 The @aa:8 addressing mode is also referred to as the short absolute addressing mode.
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3.4.3 Effective Address Calculation Table 3-8 explains how the effective address is calculated in each addressing mode. Table 3-8 Effective Address Calculation
No. 1 Addressing Mode Effective Address Calculation Register direct -- Rn 1010Sz rrr Register indirect @Rn 1101Sz rrr -- Effective Address Operand is contents of Rn
2
23 DP *1
15 Rn
0
Or TP or EP *2 3 Register indirect with displacement @(d:8,Rn) 8 Bits 15 Rn 15 0 Displacement with sign extension 16 Bits 15 Rn 15 Displacement 4 Register indirect 15 with pre-decrement @-Rn 1011Sz rrr 0 Rn 1 or 2 0
0
23 DP *1
15 Result
0
+
Or TP or EP *2
1110Sz
rrr
@(d:16,Rn) 1111Sz rrr
0
23 DP *1
15 Result
0
Or TP or EP *2
+
23 DP *1 15 Result 0
-
Or TP or EP *2
Rn is decremented by -1 or -2 before instruction execution.*3*4*5 23 DP
*1
Register indirect -- with post-increment @Rn+ Rn is incremented by +1 or +2 1100Sz rrr after instruction execution.*3*4*5 47
15 Rn
0
Or TP or EP *2
Table 3-8 Effective Address Calculation (cont)
No. 5 Addressing Mode Effective Address Calculation Absolute address -- @aa:8 0000Sz101 @aa:16 0001Sz101 6 Immediate #xx:8 00000100 #xx:16 00001100 7 -- Effective Address 23 15 0 H'00 BR EA extension data 23 DP -- 15 0 EA extension data
Operand is 1-byte EA extension data.
--
Operand is 2-byte EA extension data.
PC-relative 8 Bits disp:8 15 0 No EA code PC Specified in OP code 15 0 Displacement with sign extension disp:16 16 Bits No EA code 15 Specified in OP code PC 15 Displacement
23 CP *1
15 Result
0
23 0 CP *1
15 Result
0
0
Notes: * 1 The page register is ignored in minimum mode. * 2 The page register used in addressing modes 2, 3, and 4 depends on the general register : DP for R0, R1, R2, or R3; EP for R4 or R5; TP for R6 or R7. * 3 Decrement by -1 for a byte operand, and by -2 for a word operand. * 4 The pre-decrement or post-increment is always 2 when R7 is specified, even if the operand is byte size. * 5 The drawing below shows what happens when the @-SP and @ SP+ addressing modes are used to save and restore the stack pointer.
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SP
Old SP-2 (upper byte) Old SP-2 (lower byte)
SP
SP MOV.W SP, @-SP MOV.W @SP+.SP
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3.5 Instruction Set
3.5.1 Overview The main features of the CPU instruction set are: * A general-register architecture. * Orthogonality. Addressing modes and data sizes can be specified independently in each instruction. * 1.5 addressing modes (supporting register-register and register-memory operations) * Affinity for high-level languages, particularly C, with short formats for frequently-used instructions and addressing modes. * Standard mnemonics, common throughout the H Series. The CPU instruction set includes 63 types of instructions, listed by function in table 3-9. Table 3-9 Instruction Classification
Function Data transfer Arithmetic operations Instructions MOV, LDM, STM, XCH, SWAP, MOVTPE, MOVFPE ADD, SUB, ADDS, SUBS, ADDX, SUBX, DADD, DSUB, MULXU, DIVXU, CMP, EXTS, EXTU, TST, NEG, CLR, TAS AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BTST, BNOT Bcc*, JMP, PJMP, BSR, JSR, PJSR, RTS, PRTD, PRTS, RTD, SCB (/F, /NE, /EQ) TRAPA, TRAP/VS, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP, LINK, UNLK Total Types 7 17
Logic operations Shift Bit manipulation Branch System control
4 8 4 11 12 63
* Bcc is a conditional branch instruction in which cc represents a condition code. Tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. The MOV, ADD, and CMP instructions have special short formats, which are listed in table 3-17. For detailed descriptions of the instructions, refer to the H8/500 Series Programming Manual. The notation used in tables 3-10 to 3-17 is defined below.
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Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR CR Control register PC Program counter CP Code page register SP Stack pointer FP Frame pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move Exchange Not
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3.5.2 Data Transfer Instructions Table 3-10 describes the seven data transfer instructions. Table 3-10 Data Transfer Instructions
Instruction Data MOV transfer MOV:G MOV:E MOV:I MOV:F MOV:L MOV:S LDM STM XCH SWAP MOVTPE Size* B/W B W B/W B/W B/W W W W B B Function (EAs) (EAd), #IMM (EAd) Moves data between two general registers, or between a general register and memory, or moves immediate data to a general register or memory.
MOVFPE
B
Stack Rn (register list) Pops data from the stack to one or more registers. Rn (register list) stack Pushes data from one or more registers onto the stack. Rs Rd Exchanges data between two general registers. Rd (upper byte) Rd (lower byte) Exchanges the upper and lower bytes in a general register. Rn (EAd) Transfers data from a general register to memory in synchronization with the E clock. (EAs) Rd Transfers data from memory to a general register in synchronization with the E clock.
Note: B--byte; W--word
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3.5.3 Arithmetic Instructions Table 3-11 describes the 17 arithmetic instructions. Table 3-11 Arithmetic Instructions
Instruction Arithmetic ADD operations ADD:G ADD:Q SUB ADDS SUBS ADDX SUBX Size B/W B/W B/W B/W B/W B/W B/W Function Rd (EAs) Rd, (EAd) #IMM (EAd) Performs addition or subtraction on data in a general register and data in another general register or memory, or on immediate data and data in a general register or memory.
DADD DSUB MULXU
B B B/W
DIVXU
B/W
CMP CMP:G CMP:E CMP:I Note: B--byte; W--word
B/W B W
Rd (EAs) C Rd Performs addition or subtraction with carry or borrow on data in a general register and data in another general register or memory, or on immediate data and data in a general register or memory. (Rd)10 (Rs)10 C (Rd)10 Performs decimal addition or subtraction on data in two general registers. Rd x (EAs) Rd Performs 8-bit x 8-bit or 16-bit x 16-bit unsigned multiplication on data in a general register and data in another general register or memory, or on data in a general register and immediate data. Rd / (EAs) Rd Performs 16-bit / 8-bit or 32-bit / 16-bit unsigned division on data in a general register and data in another general register or memory, or on data in a general register and immediate data. Rn - (EAs), (EAd) - #IMM Compares data in a general register with data in another general register or memory, or with immediate data, or compares immediate data with data in memory.
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Table 3-11 Arithmetic Instructions (cont)
Instruction Arithmetic operations Size B Function ( of ) ( of ) Converts byte data in a general register to word data by extending the sign bit. 0 ( of ) Converts byte data in a general register to word data by padding with zero bits. (EAd) - 0 Compares general register or memory contents with 0. 0 - (EAd) (EAd) Obtains the two's complement of general register or memory contents. 0 (EAd) Clears general register or memory contents to 0. (EAd) -- 0, (1)2 ( of ) Tests general register or memory contents, then sets the most significant bit (bit 7) to "1."
EXTS
EXTU
B
TST NEG
B/W B/W
CLR TAS
B/W B
Note: B--byte; W--word
3.5.4 Logic Operations Table 3-12 lists the four instructions that perform logic operations. Table 3-12 Logic Operation Instructions
Instruction Logical operations Size B/W Function Rd(EAs) Rd Performs a logical AND operation on a general register and another general register, memory, or immediate data. Rd(EAs) Rd Performs a logical OR operation on a general register and another general register, memory, or immediate data. Rd(EAs) Rd Performs a logical exclusive OR operation on a general register and another general register, memory, or immediate data. (EAd) (EAd) Obtains the one's complement of general register or memory contents.
AND
OR
B/W
XOR
B/W
NOT
B/W
Note: B--byte; W--word
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3.5.5 Shift Operations Table 3-13 lists the eight shift instructions. Table 3-13 Shift Instructions
Instruction Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: B--byte; W--word Size B/W B/W B/W B/W B/W B/W B/W B/W Function (EAd) shift (EAd) Performs an arithmetic shift operation on general register or memory contents. (EAd) shift (EAd) Performs a logical shift operation on general register or memory contents. (EAd) shift (EAd) Rotates general register or memory contents. (EAd) rotate through carry (EAd) Rotates general register or memory contents through the C (carry) bit.
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3.5.6 Bit Manipulations Table 3-14 describes the four bit-manipulation instructions. Table 3-14 Bit-Manipulation Instructions
Instruction Bit BSET manipulations Size B/W Function ( of ) Z, 1 ( of ) Tests a specified bit in a general register or memory, then sets the bit to "1." The bit is specified by a bit number given in immediate data or a general register. ( of ) Z, 0 ( of ) Tests a specified bit in a general register or memory, then clears the bit to "0." The bit is specified by a bit number given in immediate data or a general register. ( of ) Z, ( of ) Tests a specified bit in a general register or memory, then inverts the bit. The bit is specified by a bit number given in immediate data or a general register. ( of ) Z Tests a specified bit in a general register or memory. The bit is specified by a bit number given in immediate data or a general register.
BCLR
B/W
BNOT
B/W
BTST
B/W
Note: B--byte; W--word
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3.5.7 Branching Instructions Table 3-15 describes the 11 branching instructions. Table 3-15 Branching Instructions
Instruction Branch Bcc Size -- Function Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP PJMP BSR JSR PJSR RTS -- -- -- -- -- -- Description Always (true) Never (false) High Low or Same Carry Clear (High or Same) Carry Set (Low) Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition True False CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
Branches unconditionally to a specified address in the same page. Branches unconditionally to a specified address in a specified page. Branches to a subroutine at a specified address in the same page. Branches to a subroutine at a specified address in the same page. Branches to a subroutine at a specified address in a specified page. Returns from a subroutine in the same page.
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Table 3-15 Branching Instructions (cont)
Instruction Branch PRTS RTD PRTD SCB/F SCB/NE SCB/EQ Size -- -- -- -- -- -- Function Returns from a subroutine in a different page. Returns from a subroutine in the same page and adjusts the stack pointer. Returns from a subroutine in a different page and adjusts the stack pointer. Controls a loop using a loop counter and/or a specified termination condition.
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3.5.8 System Control Instructions Table 3-16 describes the 12 system control instructions. Table 3-16 System Control Instructions
Instruction System TRAPA control TRAP/VS RTE LINK UNLK SLEEP LDC Size -- -- -- -- -- -- B/W* Function Generates a trap exception with a specified vector number. Generates a trap exception if the V bit is set to "1" when the instruction is executed. Returns from an exception-handling routine. FP @-SP; SP FP; SP + #IMM SP Creates a stack frame. FP SP; @SP+ FP Deallocates a stack frame created by the LINK instruction. Causes a transition to the power-down state. (EAs) CR Moves immediate data or general register or memory contents to a specified control register. CR (EAd) Moves control register data to a specified general register or memory location. CR #IMM CR Logically ANDs a control register with immediate data. CR #IMM CR Logically ORs a control register with immediate data. CR #IMM CR Logically exclusive-ORs a control register with immediate data. PC + 1 PC No operation. Only increments the program counter.
STC
B/W*
ANDC ORC XORC
B/W* B/W* B/W*
NOP
--
* The size depends on the control register.
When using the LDC and STC instructions to stack and unstack the BR, CCR, TP, DP, and EP control registers in the H8/500 family, note the following point. H8/500 hardware does not permit byte access to the stack. If the LDC.B or STC.B assembler mnemonic is coded with the @R7 + (@SP+) or @-R7 (@-SP) addressing mode, the stackpointer addressing mode takes precedence and hardware automatically performs word access.
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Specifically, the LDC.B and STC.B instructions are executed as follows. The following applies only to the stack-pointer addressing modes. In addressing modes that do not use the stack pointer, byte data access is performed as specified by the assembler mnemonic. (1) STC.B EP, @-SP When word data access is applied to EP, both EP and DP are accessed. This instruction stores EP at address SP (old) -2, and DP at address SP (old) -1.
Old SP - 2 Old SP - 1 Old SP Before execution EP a DP b New SP New SP + 1 New SP + 2 After execution a b
(2)
LDC.B @SP+, EP When word data access is applied to EP, both EP and DP are accessed. This instruction loads EP from address SP (old), and DP from address SP (old) +1, updating the DP value as well as the EP value.
a b EP a DP b EP a DP b After execution
Old SP Old SP + 1 Old SP + 2
New SP - 2 New SP - 1 New SP
Before execution
(3)
STC.B CCR, @-SP When word data access is applied to CCR, only CCR is accessed. This instruction stores identical CCR contents at both address SP (old) -2 and address SP (old) -1.
CCR a a b
Old SP - 2 Old SP - 1 Old SP Before execution
New SP New SP + 1 New SP + 2
After execution
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(4)
LDC.B @SP+, CCR When word data access is applied to CCR, only CCR is accessed. This instruction loads CCR from address SP (old) +1. Note that the value in address SP (old) is not loaded.
CCR Old SP Old SP + 1 Old SP + 2 Before execution a b New SP - 2 New SP - 1 New SP After execution CCR b
BR, DP, and TP are accessed in the same way as CCR. When DP is specified, both EP and DP are accessed, but when CCR, BR, DP, or TP is specified, only the specified register is accessed.
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3.5.9 Short-Format Instructions The ADD, CMP, and MOV instructions have special short formats. Table 3-17 lists these short formats together with the equivalent general formats. The short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster. Table 3-17 Short-Format Instructions and Equivalent General Formats
Short-Format Execution Equivalent GeneralExecution *2 Instruction Length States Format Instruction Length States *2 *1 ADD:Q #xx,Rd 2 2 ADD:G #xx:8,Rd 3 3 CMP:E #xx:8,Rd 2 2 CMP:G.B #xx:8,Rd 3 3 CMP:I #xx:16,Rd 3 3 CMP:G.W #xx:16,Rd 4 4 MOV:E #xx:8,Rd 2 2 MOV:G.B #xx:8,Rd 3 3 MOV:I #xx:16,Rd 3 3 MOV:G.W #xx:16,Rd 4 4 MOV:L @aa:8,Rd 2 5 MOV:G @aa:8,Rd 3 5 MOV:S Rs,@aa:8 2 5 MOV:G Rs,@aa:8 3 5 MOV:F @(d:8,R6),Rd 2 5 MOV:G @(d:8,R6),Rd 3 5 MOV:F Rs,@(d:8,R6) 2 5 MOV:G Rs,@(d:8,R6) 3 5 Notes: * 1 The ADD:Q instruction accepts other destination operands in addition to a general register, but the immediate data value (#xx) is limited to 1 or 2. * 2 Number of execution states for access to on-chip memory.
3.6 Operating Modes
The CPU operates in one of two modes: the minimum mode or the maximum mode. These modes are selected by the mode pins (MD2 to MD0 ). 3.6.1 Minimum Mode The minimum mode supports a maximum address space of 64k bytes. The page registers are ignored. Instructions that branch across page boundaries (PJMP, PJSR, PRTS, PRTD) are invalid.
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3.6.2 Maximum Mode In the maximum mode the page registers are valid, expanding the maximum address space to 1M byte. The address space is divided into 64k-byte pages. The pages are separate; it is not possible to move continuously across a page boundary. It is possible to move from one page to another with branching instructions (PJMP, PJSR, PRTS, PRTD). The TRAPA instruction and branches to interrupt-handling routines can also jump across page boundaries. It is not necessary for a program to be contained in a single 64k-byte page. When data access crosses a page boundary, the program must rewrite the page register before it can access the data in the next page. For further information on the operating modes, see section 2, "MCU Operating Modes and Address Space."
3.7 Basic Operational Timing
3.7.1 Overview The CPU operates on a system clock (o) which is created by dividing an oscillator frequency (fosc) by two. One period of the system clock is referred to as a "state." The CPU accesses memory in a cycle consisting of 2 or 3 states. The CPU uses different methods to access on-chip memory, the on-chip register field, and external devices. Access to On-Chip Memory (RAM, ROM): For maximum speed, access to on-chip memory (RAM, ROM) is performed in two states, using a 16-bit-wide data bus. Figure 3-6 shows the on-chip memory access cycle. Figure 3-7 indicates the pin states. The bus control signals output from the H8/532 chip go to the nonactive state during the access. Access to On-Chip Register Field (Addresses H'FF80 to H'FFFF): The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-8 shows the on-chip supporting module access cycle. Figure 3-9 indicates the pin states.
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Access to External Devices: The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-10 (a) and (b) shows the external access cycle. Additional wait states (Tw) can be inserted by the wait-state controller (WSC). 3.7.2 On-Chip Memory Access Cycle
Memory cycle T1 state o T2 state
Internal address bus
Address
Internal Read signal
Internal data bus (Read access) Internal Write signal
Read data
Internal data bus (Write access)
Write data
Figure 3-6 On-Chip Memory Access Timing
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3.7.3 Pin States during On-Chip Memory Access
T1 state o
T2 state
A19 to A 0
R/W (read access)
R/W (write access) "High" AS, DS, RD, WR High-impedance D 7 to D 0
Figure 3-7 Pin States during Access to On-Chip Memory
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3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF)
Memory cycle T1 state T2 state T3 state
o
Internal address bus
Address
Internal Read signal
Internal data bus (read access) Internal Write signal
Read data
Internal data bus (write access)
Write data
Figure 3-8 Register Field Access Timing
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3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF)
T1 state
T2 state
T3 state
o
A 19 to A 0
R/W (read access)
R/W (write access) "High" AS, DS, RD, WR High-impedance D 7 to D0
Figure 3-9 Pin States during Register Field Access
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3.7.6 External Access Cycle
Read cycle T1 state o T2 state T3 state
A19 -A 0
Address
AS
R/W
DS
RD "High" WR
D7 -D0
Read data
Figure 3-10 (a) External Access Cycle (Read Access)
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Write cycle T1 state o T2 state T3 state
A19 -A 0
Address
AS
R/W
DS "High" RD
WR
D7 -D0
Write data
Figure 3-10 (b) External Access Cycle (Write Access)
3.8 CPU States
3.8.1 Overview The CPU has five states: the program execution state, exception-handling state, bus-released state, reset state, and power-down state. The power-down state is further divided into the sleep mode, software standby mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a map of the state transitions.
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State
Program execution state The CPU executes program instructions in sequence.
Exception-handling state A transient state in which the CPU executes a hardware sequence (saving the program counter and status register, fetching a vector from the vector table, etc.) triggered by a reset, interrupt, or other exception.
Bus-released state The state in which the CPU has released the external bus in response to a bus request signal from an external device, and is waiting for the bus to be returned.
Reset state The state in which the CPU and all on-chip supporting modules have been initialized and are stopped.
Power-down state A state in which some or all of the clock signals are stopped to conserve power.
Sleep mode
Software standby mode
Hardware standby mode
Figure 3-11 Operating States
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BREQ = "1" BREQ = "0"
Program execution state SLEEP SLEEP instruction instruction with standby flag set Sleep mode
BREQ = "1"
BREQ = "0" End of exception handling Request for exception handling
Bus-released state
Interrupt request Exception-handling state RES = "1" NMI Software standby mode
Reset state * 1
STBY = "1", RES = "0"
Hardware standby mode
*2
* 1 From any state except the hardware standby mode, a transition to the reset state occurs whenever RES goes Low. * 2 A transition to the hardware standby mode from any state occurs when STBY goes Low.
Figure 3-12 State Transitions 3.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 3.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to an interrupt, trap instruction, address error, or other exception. In this state the CPU carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine.
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In the hardware exception-handling sequence the CPU does the following: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to "0." 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address, returning to the program execution state. See section 4, "Exception Handling," for further information on the exception-handling state. 3.8.4 Bus-Released State When so requested, the CPU can grant control of the external bus to an external device. While an external device has the bus right, the CPU is said to be in the bus-released state. The bus right is controlled by two pins: * BREQ: * BACK: Input pin for the Bus Request signal from an external device Output pin for the Bus Request Acknowledge signal from the CPU, indicating that the CPU has released the bus
The procedure by which the CPU enters and leaves the bus-released state is: 1. The CPU receives a Low BREQ signal from an external device. 2. The CPU places the address bus pins (A19 - A0), data bus pins (D7 - D0) and bus control pins (RD, WR, R/W, DS, and AS) in the high-impedance state, sets the BACK pin to the Low level to indicate that it has released the bus, then halts. 3. The external device that requested the bus (with the BREQ signal) becomes the bus master. It can use the data bus and address bus. The external device is responsible for manipulating the bus control signals (RD, WR, R/W, DS, and AS). 4. When the external device finishes using the bus, it clears the BREQ signal to the High level. The CPU then reassumes control of the bus and returns to the program execution state. Bus Release Timing: The CPU can release the bus right at the following times: 1. The BREQ signal is sampled during every memory access cycle (instruction prefetch or data read/write). If BREQ is Low, the CPU releases the bus right at the end of the cycle. (In word data access to external memory or an address from H'FF80 to H'FFFF, the CPU does not release the bus right until it has accessed both the upper and lower data bytes.) 2. During execution of the MULXU and DIVXU instructions, since considerable time may pass without an instruction prefetch or data read/write, BREQ is also sampled at internal machine cycles, and the bus right is released if BREQ is Low. 3. The bus right can also be released in the sleep mode. The CPU does not recognize interrupts while the bus is released.
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Timing Charts: Timing charts of the operation by which the bus is released are shown in figure 3-13 for the case of bus release during an on-chip memory read cycle, in figure 3-14 for bus release during an external memory read cycle, and in figure 3-15 for bus release while the CPU is performing an internal operation.
On-chip memory Access cycle
Bus-right release cycle
CPU cycle
T2 o
T1*
T2*
TX*
TX
TX
TX
T1
A19 -A 0
D7 -D0
RD, WR, R/W DS, AS
BREQ
BACK
(1)
(2)
(3)
(4)
(5)
(1) (2) (3) (4) (5)
The BREQ pin is sampled at the start of the T1 state and the Low level is detected. At the end of the memory access cycle, the BACK pin goes Low and the CPU releases the bus. While the bus is released, the BREQ pin is sampled at each Tx state. A High level is detected at the BREQ pin. The BACK pin is returned to the High level, ending the bus-right release cycle.
Fig. 3-13
* T1 and T2: On-chip memory access states. Tx : Bus-right released state.
Figure 3-13 Bus-Right Release Cycle (During On-Chip Memory Access Cycle)
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External access cycle
Bus-right release cycle
CPU cycle
T1 o
T2
TW*
T3
TX*
TX
TX
T1
A19 -A 0
D7 -D0
RD, WR R/W, DS
BREQ
BACK (1) (2) (3) (4)
(1) (2) (3) (4)
The BREQ pin is sampled at the start of the TW state and the Low level is detected. At the end of the external access cycle, the BACK pin goes Low and the CPU releases the bus. The BREQ pin is sampled at the TX state and a High level is detected. The BACK pin is returned to the High level, ending the bus-right release cycle.
* TW : Wait state. TX : Bus-right released state.
Fig. 3-14
Figure 3-14 Bus-Right Release Cycle (During External Access Cycle)
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External access cycle
Bus-right release cycle
CPU cycle
Ti * o
Ti
Ti
Ti
TX*
TX
TX
T1
A19 -A 0
D7 -D0
RD, WR R/W, DS
BREQ
BACK (1) (2) (3) (4)
(1) (2) (3) (4)
The BREQ pin is sampled at the start of a TI state and the Low level is detected. At the end of the internal operation cycle, the BACK pin goes Low and the CPU releases the bus. The BREQ pin is sampled at the TX state and a High level is detected. The BACK pin is returned to the High level, ending the bus-right release cycle.
Fig. 3-15
* TI : Internal CPU operation state. TX : Bus-right released state.
Figure 3-15 Bus-Right Release Cycle (During Internal CPU Operation)
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Notes: The BREQ signal must be held Low until BACK goes Low. If BREQ returns to the High level before BACK goes Low, the bus release operation may be executed incorrectly. To leave the bus-released state, the High level at the BREQ pin must be sampled two times. If the BREQ returns to Low before it is sampled two times, the bus released cycle will not end. The bus release operation is enabled only when the BRLE bit in the port 1 control register (P1CR) is set to "1." When this bit is cleared to "0" (its initial value), the BREQ and BACK pins are used for general-purpose input and output, as P13 and P12. An instruction that sets the BRLE bit is: BSET.B #3, @H'FFFC Note the following point when using the H8/532's release function. If the BREQ signal is asserted and an interrupt is requested simultaneously during execution of the SLEEP instruction, the BACK signal may fail to be output even though the CPU has released the bus. This may cause the system to stop for the interval during which BREQ is asserted, with no device in control of the bus. The interrupts that can cause this state include NMI, IRQ, and all the interrupts from on-chip supporting modules. When the BREQ signal is deasserted, ending this state, the CPU takes control of the bus again and resumes normal instruction execution. The following methods can be used to avoid entering this state. Method 1: If the BREQ signal is used, do not use the SLEEP instruction. Method 2: Disable the BREQ signal during execution of the SLEEP instruction. This can be done by clearing the bus release enable bit (BRLE) in the port 1 control register (P1CR) to 0 immediately bifore executing the SLEEP instruction. (When the BRLE bit is cleared, low inputs on the BREQ line are not latched on-chip.) Place instructions to set the BRLE bit to 1 at the beginning of interrupt-handling routines. If the data transfer controller (DTC) is used, place an instruction to set the BRLE bit immediately after the SLEEP instruction. If method 2 is used, BREQ inputs will be ignored while the chip is in sleep mode. (Coding example) Main Program BCLR.B SLEEP BSET.B #3, @P1CR #3, @P1CR RTE
Interrupt-Handling Routine BSET.B #3, @P1CR
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3.8.5 Reset State In the reset state, the CPU and all on-chip supporting modules are initialized and placed in the stopped state. The CPU enters the reset state whenever the RES pin goes Low, unless the CPU is currently in the hardware standby mode. It remains in the reset state until the RES pin goes High. See section 4.2, "Reset," for further information on the reset state. 3.8.6 Power-Down State The power-down state comprises three modes: the sleep mode, the software standby mode, and the hardware standby mode. See section 18, "Power-Down State," for further information.
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3.9 Programming Notes
3.9.1 Restriction on Address Location The following restriction applies when instructions are located in on-chip RAM. * Restriction Instruction execution cannot proceed continuously from an external address to on-chip RAM in the ZTAT versions. This restriction does not apply to versions with masked ROM. * Solution To execute instructions located in on-chip RAM, use a branch instruction (examples: Bcc, JMP, etc.) to branch to the first instruction located in on-chip RAM. Do not place instruction code in the last three bytes of external memory (H'FB7D to H'FB7F).
H'FB7A H'FB7B H'FB7C H'FB7D H'FB7E H'FB7F H'FB80 H'FB81
NOP NOP NOP NOP NOP NOP NOP NOP Not executable
H'FB7A H'FB7B H'FB7C H'FB7D H'FB7E H'FB7F H'FB80 H'FB81
NOP BRA disp Do not place instruction code here NOP NOP
Branch
Execution Disabled
Execution Enabled
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3.9.2 Note on MULXU Instruction Note that in the case described below, the H8/532 multiply instruction does not give correct results. (1) Problem The result of a squaring operation such as MULXU.B Rn, Rn is indeterminate. This problem occurs when the same register is specified for the source and destination of a byte multiplication operation. This problem occurs only in ZTAT versions of the H8/532. It does not occur in versions with masked ROM. (2) Solution The problem can be avoided by the following methods. Place the source and destination operands in different registers. Example: MULXU.B R4, R4 MOV.W R4, R5 MULXU.B R5, R4 Use a word multiplication instruction. Example: MULXU.B R4, R4
MULXU.W R4, R4 MOV.W R5, R4
Place one of the operands in memory. Example: MULXU.B R4, R4
MOV.W R4, @-SP MULXU.B @(1,SP), R4 ADDS #2, SP
This problem occurs only in the H8/532. It does not occur in other chips in the H8/500 Series (such as the H8/520). (3) Note on usage of C compiler
Programmers using the C compiler should bear the following programming note in mind. * Conditions under which the compiler generates a MULXU.B Rn, Rn instruction The C compiler generates a MULXU.B Rn, Rn instruction when the following two conditions are satisfied in the source program:
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A one-byte variable (char or unsigned char) is declared as a register variable. The variable declared as in is squared by compound substitution Example: register char a; a *= a; * Solution The problem can be avoided as follows: In the example above, do not declare the variable (a) as a register variable. Example: register char a; char a; a *= a; a *= a; When squaring one-byte data, do not use compound substitution. Code as follows: Example: a *= a; a = a * a;
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Section 4 Exception Handling
4.1 Overview
4.1.1 Types of Exception Handling and Their Priority As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error, trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor. Exception handling begins with a hardware exception-handling sequence which prepares for the execution of a user-coded software exception-handling routine. There is a priority order among the different types of exceptions, as shown in table 4-1 (a). If two or more exceptions occur simultaneously, they are handled in their order of priority. An instruction exception cannot occur simultaneously with other types of exceptions. Table 4-1 (a) Exceptions and Their Priority
Exception Type High Reset Address error Trace Interrupt Low Source External Internal Internal External, internal Detection Timing RES Low-to-High transition Instruction fetch or data read/write bus cycle End of instruction execution, if T = "1" in status register End of instruction execution or end of exception-handling sequence Start of ExceptionHandling Sequence Immediately End of instruction execution End of instruction execution End of instruction execution
Table 4-1 (b) Instruction Exceptions
Exception Type Invalid instruction Trap instruction Zero divide Start of Exception-Handling Sequence Attempted execution of instruction with undefined code Started by execution of trap instruction Attempted execution of DIVXU instruction with zero divisor
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4.1.2 Hardware Exception-Handling Sequence The hardware exception-handling sequence varies depending on the type of exception. When exception handling is initiated by a factor other than a reset, the CPU: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to "0." 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address. For an interrupt, the CPU also alters the interrupt mask level in bits I2 to I0 of the status register. For a reset, step 1 is omitted. See section 4.2, "Reset," for the full reset sequence. 4.1.3 Exception Factors and Vector Table The factors that initiate exception handling can be classified as shown in figure 4-1. The starting addresses of the exception-handling routines for each factor are contained in an exception vector table located in the low addresses of page 0. The vector addresses are listed in table 4-2. Note that there are different addresses for the minimum and maximum modes.
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* Reset External interrupt NMI IRQ0 IRQ1 * Interrupt
Internal interrupt
Internal interrupt requested by on-chip module
Exception
* Address error
* Trace
Invalid instruction * Instruction Zero divide TRAPA instruction TRAP/VS instruction
Figure 4-1 Types of Factors Causing Exception Handling
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Table 4-2 Exception Vector Table
Vector Address Maximum Mode *1 H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 to H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 to H'003C to H'003F H'0040 to H'0043 to H'007C to H'007F H'0080 to H'0083 H'0084 to H'0087 H'0088 to H'008B to H'00FC to H'00FF
Type of Exception Reset (initialize PC) -- (Reserved for system) Invalid instruction DIVXU instruction (zero divide) TRAP/VS instruction -- (Reserved for system) Address error Trace -- (Reserved for system) Nonmaskable external interrupt (NMI) -- (Reserved for system) TRAPA instruction (16 vectors)
External interrupts Internal interrupts *2
IRQ0 IRQ1
Minimum Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B to H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 to H'001E to H'001F H'0020 to H'0021 to H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 to H'007E to H'007F
Notes: * 1. The exception vector table is located at the beginning of page 0. * 2. For details of the internal interrupt vectors, see table 5-2.
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4.2 Reset
4.2.1 Overview A reset has the highest exception-handling priority. When the RES pin goes Low, all current processing is halted and the H8/532 chip enters the reset state. A reset initializes the internal status of the CPU and the registers of the on-chip supporting modules and I/O ports. It does not initialize the on-chip RAM. When the RES pin returns from Low to High, the H8/532 chip comes out of the reset state and begins executing the hardware reset sequence. 4.2.2 Reset Sequence The Reset signal is detected when the RES pin goes Low. To ensure that the H8/532 is reset, the RES pin should be held Low for at least 20ms at power-up. To reset the H8/532 during operation, the RES pin should be held Low for at least 6 o clock cycles. See table D-1, "Status of Ports" in Appendix D for the status of other pins in the reset state. When the RES pin returns to the High state after being held Low for the necessary time, the hardware reset exception-handling sequence begins, during which: 1. The value at the mode pins (MD2 to MD0) is latched in bits MDS2 to MDS0 of the mode control register (MDCR). 2. In the status register (SR), the T bit is cleared to disable the trace mode, and the interrupt mask level (bits I2 to I0) is set to 7. A reset disables all interrupts, including NMI. 3. The CPU loads the reset start address from the vector table into the program counter and begins executing the program at that address. The contents of the vector table differs between minimum mode and maximum mode as indicated in figure 4-2. This affects step 3 as follows: Minimum mode: One word is copied from addresses H'0000 and H'0001 in the vector table to the program counter. Program execution then begins from the address in the program counter (PC).
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Maximum Mode: Two words are read from addresses H'0000 to H'0003 in the vector table. The byte in address H'0000 is ignored. The byte in address H'0001 is copied to the code page register (CP). The contents of addresses H'0002 and H'0003 are copied to the program counter. Program execution starts from the address indicated by the code page register and program counter.
H'0000 H'0001
PC (Upper) PC (Lower)
H'0000 H'0001 H'0002 H'0003
Don't care CP PC (Upper) PC (Lower)
(1) Minimum mode
(2) Maximum mode
Figure 4-2 Reset Vector Figure 4-3 shows the timing of the reset sequence in minimum mode. Figure 4-4 shows the timing of the reset sequence in maximum mode. 4.2.3 Stack Pointer Initialization The hardware reset sequence does not initialize the stack pointer, so this must be done by software. If an interrupt were to be accepted after a reset and before the stack pointer (SP) is initialized, the program counter and status register would not be saved correctly, causing a program crash. This danger can be avoided by coding the reset routine as explained next. When the chip comes out of the reset state all interrupts, including NMI, are disabled, so the instruction at the reset start address is always executed. In the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, this instruction should be an LDC instruction initializing the stack page register (TP), and the next instruction should initialize the stack pointer. Execution of the LDC instruction disables interrupts again, ensuring that the stack pointer initializing instruction is executed.
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o
RES
Internal address bus (1) (2)
Vector address Vector
(3)
Internal data bus (16 bits)
(4)
Internal Read signal
Fig. 4-3
Figure 4-3 Reset Sequence (Minimum Mode, On-Chip Memory)
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Minimum 6 states
Internal Write signal Internal processing cycle Reset vector Prefetch first instruction of program Instruction execution cycle
(1) Instruction prefetch address (2) Operation code
(3) Program start address (4) First instruction of program
Note: This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the program starts at an even address.
o
RES
A 23 to A 0
Vector address (1)
Vector address + 1
Vector address + 2
Vector address + 3
D15 to D0
don't care (2)
Vector CP
Vector PC H
Vector PC L
Read signal RD
Figure 4-4 Reset Sequence (Maximum Mode, External Memory)
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Internal processing cycle Reset vector (1) Program start address (2) First instruction of program
Write signal LWR, HWR
Prefetch first instruction of program
Instruction execution cycle
Note: This diagram applies to maximum mode when the program area and vector table are both in external memory. After a reset, the wait-state controller inserts three wait states in each bus cycle.
4.3 Address Error
There are three causes of address errors: * Illegal instruction prefetch * Word data access at odd address * Off-chip access in single-chip mode An address error initiates the address error exception-handling sequence. This sequence clears the T bit of the status register to "0" to disable the trace mode, but does not affect the interrupt mask level in bits I2 to I0. 4.3.1 Illegal Instruction Prefetch An attempt to prefetch an instruction from the register field in memory addresses H'FF80 to H'FFFF causes an address error regardless of the MCU operating mode. Handling of this address error begins when the prefetch cycle that caused the error has been completed and execution of the current instruction has also been completed. The program counter value pushed on the stack is the address of the instruction immediately following the last instruction executed. Program code should not be located in addresses H'FF7D to H'FF7F. If the CPU executes an instruction in these addresses, it will attempt to prefetch the next instruction from the register field, causing an address error. 4.3.2 Word Data Access at Odd Address If an attempt is made to access word data starting at an odd address, an address error occurs regardless of the MCU operating mode. The program counter value pushed on the stack in the handling of this error is the address of the next instruction (or next but one) after the instruction that attempted the illegal word access. 4.3.3 Off-Chip Address Access in Single-Chip Mode In the single-chip mode there is no external memory, so in addition to the address errors described above, the following two types of address errors can occur. Access to Addresses H'8000 to H'FB7F: These addresses exist neither in on-chip ROM or RAM nor in the on-chip register field, so an address error occurs if they are accessed for any purpose: for instruction prefetch, byte data access, or word data access.
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Access to Disabled RAM Area: The on-chip RAM area (H'FB80 to H'FF7F) can be disabled by clearing the RAME bit in the RAM control register (RAMCR). If RAM access is attempted in this state in the single-chip mode, an address error occurs.
4.4 Trace
When the T bit of the status register is set to "1," the CPU operates in trace mode. A trace exception occurs at the completion of each instruction. The trace mode can be used to execute a program for debugging by a debugger. In the trace exception sequence the T bit of the status register is cleared to "0" to disable the trace mode while the trace routine is executing. The interrupt mask level in bits I2 to I0 is not changed. Interrupts are accepted as usual during the trace routine. In the status-register data saved on the stack, the T bit is set to "1." When the trace routine returns with the RTE instruction, the status register is popped from the stack and the trace mode resumes. If an address error occurs during execution of the first instruction after the return from the trace routine, since the address error has higher priority, the address error exception-handling sequence is initiated, clearing the T bit in the status register to "0" and making it impossible to trace this instruction.
4.5 Interrupts
Interrupts can be requested from three external sources (NMI, IRQ0, and IRQ1) and seven on-chip supporting modules: the 16-bit free-running timers (FRT1 to FRT3), the 8-bit timer, the serial communication interface (SCI), the A/D converter, and the watchdog timer (WDT). The on-chip interrupt sources can request a total of nineteen different types of interrupts, each having its own interrupt vector. Figure 4-5 lists the interrupt sources and the number of different interrupts from each source. Each interrupt source has a priority. NMI interrupts have the highest priority, and are normally accepted unconditionally. The priorities of the other interrupt sources are set in control registers (IPR A to D) in the register field at the high end of page 0 and can be changed by software. Priority levels range from 0 (low) to 7 (high), with NMI considered to be on level 8. The on-chip interrupt controller decides whether an interrupt can be accepted by comparing its priority with the interrupt mask level, and determines the order in which to accept competing interrupt requests. Interrupts that are not accepted immediately remain pending until they can be accepted later.
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When it accepts an interrupt, the interrupt controller also decides whether to interrupt the CPU or start the on-chip data transfer controller (DTC). This decision is controlled by bits set in four data transfer enable registers (DTE A to D) in the register field. The DTC is started if the corresponding DTE bit is set to "1;" otherwise a CPU interrupt is generated. DTC interrupts provide an efficient way to send and receive blocks of data via the serial communication interface, or to transfer data between memory and I/O without detailed CPU programming. The CPU stops while the DTC is operating. DTC interrupts are described in section 6, "Data Transfer Controller." The hardware exception-handling sequence for a CPU interrupt clears the T bit in the status register to "0" and sets the interrupt mask level in bits I2 to I0 to the level of the interrupt it has accepted. This prevents the interrupt-handling routine from being interrupted except by a higherlevel interrupt. The previous interrupt mask level is restored on the return from the interrupthandling routine. For further information on interrupts, see section 5, "Interrupt Controller."
NMI (1) IRQ0 (1) IRQ1 (1)
External interrupts
Interrupt sources 16-Bit FRT1 (4) 16-Bit FRT2 (4) 16-Bit FRT3 (4) Internal interrupts 8-Bit timer (3) SCI (3) A/D converter (1) NMI: IRQ: FRT: SCI: WDT: NonMaskable Interrupt Interrupt Request Free-Running Timer Serial Communication Interface WatchDog Timer WDT*
* Interrupts from the watchdog timer are handled as NMI or IRQ0.
Figure 4-5 Interrupt Sources (and Number of Interrupt Types)
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4.6 Invalid Instruction
An invalid instruction exception occurs if an attempt is made to execute an instruction with an undefined operation code or illegal addressing mode specification. The program counter value pushed on the stack is the value of the program counter when the invalid instruction code was detected. In the invalid instruction exception-handling sequence the T bit of the status register is cleared to "0," but the interrupt mask level (I2 to I0) is not affected.
4.7 Trap Instructions and Zero Divide
A trap exception occurs when the TRAPA or TRAP/VS instruction is executed. A zero divide exception occurs if an attempt is made to execute a DIVXU instruction with a zero divisor. In the exception-handling sequences for these exceptions the T bit of the status register is cleared to "0," but the interrupt mask level (I2 to I0) is not affected. If a normal interrupt is requested while a trap or zero-divide instruction is being executed, after the trap or zero-divide exceptionhandling sequence, the normal interrupt exception-handling sequence is carried out. TRAPA Instruction: The TRAPA instruction always causes a trap exception. The TRAPA instruction includes a vector number from 0 to 15, allowing the user to provide up to sixteen different trap-handling routines. TRAP/VS Instruction: When the TRAP/VS instruction is executed, a trap exception occurs if the overflow (V) bit in the condition code register is set to "1." If the V bit is cleared to "0," no exception occurs and the next instruction is executed. DIVXU Instruction with Zero Divisor: An exception occurs if an attempt is made to divide by zero in a DIVXU instruction.
4.8 Cases in Which Exception Handling is Deferred
In the cases described next, the address error exception, trace exception, external interrupt (NMI, IRQ0, and IRQ1) requests, and internal interrupt requests (19 types) are not accepted immediately but are deferred until after the next instruction has been executed. 4.8.1 Instructions that Disable Interrupts Interrupts are disabled immediately after the execution of five instructions: XORC, ORC, ANDC, LDC, and RTE. Suppose that an internal interrupt is requested and the interrupt controller, after checking the interrupt priority and interrupt mask level, notifies the CPU of the interrupt, but the CPU is
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currently executing one of the five instructions listed above. After executing this instruction the CPU always proceeds to the next instruction. (And if the next instruction is one of these five, the CPU also proceeds to the next instruction after that.) The exception-handling sequence starts after the next instruction that is not one of these five has been executed. The following is an example: (Example)
Program flow
. . . . . .
LDC.B #H'00,TP
Interrupt controller notifies CPU of interrupt request CPU executes the instruction next to LDC before starting exception handling
MOV.W #H'FF80,SP
MOV.B #H'00,@WCR
. . .
To exception-handling sequence
4.8.2 Disabling of Exceptions Immediately after a Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the program counter and status register will not be saved correctly, leading to a program crash. To prevent this, when the chip comes out of the reset state all interrupts, including the NMI, are disabled, so the first instruction of the reset routine is always executed. As noted earlier, in the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, the first instruction should be an LDC instruction that initializes the stack page register (TP); the next instruction should initialize the stack pointer. 4.8.3 Disabling of Interrupts after a Data Transfer Cycle If an interrupt starts the data transfer controller and another interrupt is requested during the data transfer cycle, when the data transfer cycle ends, the CPU always executes the next instruction before handling the second interrupt. Even if a nonmaskable interrupt (NMI) occurs during a data transfer cycle, it is not accepted until the next instruction has been executed. An example of this is shown below.
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(Example)
. . . . . Program flow
ADD.W R2,R0
DTC interrupt request Data transfer cycle NMI interrupt request
MOV.W R0,@H'FF00
After data transfer cycle, CPU executes next instruction before branching to exception handling To NMI exception-handling sequence
MOV.W #H'FF02,R0
. . .
4.9 Stack Status after Completion of Exception Handling
The status of the stack after an exception-handling sequence is described below. Table 4-3 shows the stack after completion of the exception-handling sequence for various types of exceptions in the minimum and maximum modes. Table 4-3 Stack after Exception Handling Sequence
Exception Factor Minimum Mode Maximum Mode
Trace Interrupt Trap Zero divide (DIVXU)
SP
SR (upper byte) SR (lower byte) Next instruction address (upper byte) Next instruction address (lower byte)
TP:SP
SR (upper byte) SR (lower byte) Don't-care Next instruction page (8 bits) Next instruction address (upper byte) Next instruction address (lower byte)
Note: The RTE instruction returns to the next instruction after the instruction being executed when the exception occurred.
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Table 4-3 Stack after Exception Handling Sequence (cont)
Exception Factor Minimum Mode Maximum Mode
Invalid instruction
SP
SR (upper byte) SR (lower byte) PC when error occurred (upper byte) PC when error occurred (lower byte)
TP:SP
SR (upper byte) SR (lower byte) Don't-care CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is not necessarily the address of the first byte of the invalid instruction.
Address error
SP
SR (upper byte) SR (lower byte) PC when error occurred (upper byte) PC when error occurred (lower byte)
TP:SP
SR (upper byte) SR (lower byte) Don't-care CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is the address of the next instruction after the last instruction successfully executed.
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4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions The program counter value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt was accepted. The RTE instruction accordingly returns to the next instruction after the instruction executed before the exception-handling sequence. 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions The program counter value pushed on the stack for an address error or invalid instruction exception differs depending on the conditions when the exception occurred.
4.10 Notes on Use of the Stack
If the stack pointer is set to an odd address, an address error will occur when the stack is accessed during interrupt handling or for a subroutine call. The stack pointer should always point to an even address. To keep the stack pointer pointing to an even address, a program should use word data size when saving or restoring registers to and from the stack. In the @-SP or @SP+ addressing mode, the CPU performs word access even if the instruction specifies byte size. (This is not true in the @-Rn and @Rn+ addressing modes when Rn is a register from R0 to R6.)
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Section 5 Interrupt Controller
5.1 Overview
The interrupt controller decides which interrupts to accept, and how to deal with multiple interrupts. It also decides whether an interrupt should be served by the CPU or by the data transfer controller (DTC). This section explains the features of the interrupt controller, describes its internal structure and control registers, and details the handling of interrupts. For detailed information on the data transfer controller, see section 6, "Data Transfer Controller." 5.1.1 Features Three main features of the interrupt controller are: * Interrupt priorities are user-programmable. User programs can set priority levels from 7 (high) to 0 (low) in four interrupt priority (IPR) registers for IRQ0, IRQ1, and each of the on-chip supporting modules--for every interrupt, that is, except the nonmaskable interrupt (NMI). NMI has the highest priority level (8) and is normally always accepted. An interrupt with priority level 0 is always masked. * Multiple interrupts on the same level are served in a default priority order. Lower-priority interrupts remain pending until higher-priority interrupts have been handled. * For most interrupts, software can select whether to have the interrupt served by the CPU or the on-chip data transfer controller (DTC). User programs can make this selection by setting and clearing bits in four data transfer enable (DTE) registers. The data transfer controller can be started by any interrupts except NMI, the error interrupt (ERI) from the on-chip serial communication interface, and the overflow interrupts (FOVI and OVI) from the on-chip timers.
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5.1.2 Block Diagram Figure 5-1 shows the block configuration of the interrupt controller.
Interrupt controller NMI IRQ0 IRQ1 IPRA to IPRD FRT1 Interrupt request signals from modules FRT2 FRT3 8 bits timer SCI A/D converter Priority decision NMI request
Comparator
Interrupt request
DTEA to DTED
DTC request
I2 FRT: 16 Bits Free Running Timer SCI: Serial Communication Interface SR: Status Register IPR: Interrupt Priority Register DTE: Data Transfer Enable Register
I1
I0
SR (CPU)
Figure 5-1 Interrupt Controller Block Diagram
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5.1.3 Register Configuration The four interrupt priority registers (IPRA to IPRD) and four data transfer enable registers (DTEA to DTED) are 8-bit registers located at addresses H'FFF0 to H'FFF7 in the register field in page 0 of the address space. Table 5-1 lists their attributes. Table 5-1 Interrupt Controller Registers
Name Interrupt priority register Data transfer enable register A B C D A B C D Abbreviation IPRA IPRB IPRC IPRD DTEA DTEB DTEC DTED Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Address H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
5.2 Interrupt Types
There are 22 distinct types of interrupts: 3 external interrupts originating off-chip and 19 internal interrupts originating in the on-chip supporting modules. 5.2.1 External Interrupts The three external interrupts are NMI, IRQ0, and IRQ1. NMI (NonMaskable Interrupt): This interrupt has the highest priority level (8) and cannot be masked. An NMI is generated by input to the NMI pin, and can also be generated by a watchdog timer (WDT) overflow. The input at the NMI pin is edge-sensed. A user program can select whether to have the interrupt occur on the rising edge or falling edge of the NMI input by setting or clearing the nonmaskable interrupt edge bit (NMIEG) in the port 1 control register (P1CR). In the NMI exception-handling sequence, the T (Trace) bit in the CPU status register (SR) is cleared to "0," and the interrupt mask level in I2 to I0 is set to 7, masking all other interrupts. The interrupt controller holds the NMI request until the NMI exception-handling sequence begins, then clears the NMI request, so if another interrupt is requested at the NMI pin during the NMI exception-handling sequence, the NMI exception-handling sequence will be carried out again. A watchdog timer overflow generates an NMI if the TME and WT/IT bits in the watchdog timer's status/control register are both set to "1." See section 13, "Watchdog Timer" for details.
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Coding Examples: To select the rising edge of the NMI input: To select the falling edge of the NMI input:
BSET.B #4, @H'FFFC BCLR.B #4, @H'FFFC
IRQ0 (Interrupt Request 0): An IRQ0 interrupt can be requested by a Low input to the IRQ0 pin and/or a watchdog timer overflow. A Low IRQ0 input requests an IRQ0 interrupt if the interrupt request enable 0 bit (IRQ0E) in the P1CR is set to "1." IRQ0 must be held Low until the CPU accepts the interrupt. Otherwise the request will be ignored. A watchdog timer overflow requests an IRQ0 interrupt if the TME bit is set to "1" and the WT/IT bit is cleared to "0" in the watchdog timer's control/status register. See section 13, "Watchdog Timer" for details of the watchdog timer. The IRQ0 interrupt can be assigned any priority level from 7 to 0 by setting the corresponding value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to "1," an IRQ0 interrupt starts the data transfer controller. Otherwise the interrupt is served by the CPU. In the CPU interrupt-handling sequence for IRQ0, the T bit of the status register is cleared to "0," and the interrupt mask level is set to the value in the upper four bits of IPRA. Coding Examples: To enable IRQ0 to be requested by IRQ0 input: To assign priority level 7 to IRQ0: To have IRQ0 start the DTC:
BSET.B #5, @H'FFFC OR.B #70, @H'FFF0 BSET.B #4, @H'FFF4
IRQ1 (Interrupt Request 1): An IRQ0 interrupt is requested by a High-to-Low transition at the IRQ1 pin. The IRQ1 interrupt is enabled only when the interrupt request enable 1 bit (IRQ1E) in the P1CR is set to "1." The IRQ1 interrupt can be assigned any priority level from 7 (high) to 0 (low) by setting the corresponding value in the lower four bits of IPRA. If bit 0 of data transfer enable register A (DTEA) is set to "1," an IRQ1 interrupt starts the data transfer controller. Otherwise the interrupt is served by the CPU. The interrupt controller holds the IRQ1 request until the IRQ1 exception-handling sequence begins, then clears the IRQ1 request. If another interrupt is requested at the IRQ1 pin during the IRQ1 interrupt-handling routine, the request is held, but the IRQ1 exception-handling sequence is not carried out immediately because the interrupt is masked by bits I2 to I0 in the status register. On return from the interrupt-handling routine one more instruction is executed, then the exception-handling sequence for the second IRQ1 interrupt is carried out.
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In the CPU interrupt-handling sequence for IRQ1, the T bit of the CPU status register is cleared to "0," and the interrupt mask level is set to the value in the lower four bits of IPRA. Coding Examples: To enable IRQ1 to be requested by IRQ1 input: To assign priority level 7 to IRQ0 and level 5 to IRQ1: To have IRQ1 start the DTC: 5.2.2 Internal Interrupts Nineteen types of internal interrupts can be requested by the on-chip supporting modules. Each interrupt is separately vectored in the exception vector table, so it is not necessary for the usercoded interrupt handler routine to determine which type of interrupt has occurred. Each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the control register of the on-chip supporting module. An interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by setting interrupt priority registers B to D. Within each module, different interrupts have a fixed priority order. For most of these interrupts, values set in data transfer enable registers B to D can select whether to have the interrupt served by the CPU or the data transfer controller. In the CPU interrupt-handling sequence, the T bit of the CPU status register is cleared to "0," and the interrupt mask level in bits I2 to I0 is set to the value in the IPR. 5.2.3 Interrupt Vector Table Table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains how their priority is determined. For the on-chip supporting modules, the priority level set in the interrupt priority register applies to the module as a whole: all interrupts from that module have the same priority level. A separate priority order is established among interrupts from the same module. If the same priority level is assigned to two or more modules and two interrupts are requested simultaneously from these modules, they are served in the priority order indicated in the rightmost column in table 5-2. A reset clears the interrupt priority registers so that all interrupts except NMI start with priority level 0, meaning that they are unconditionally masked.
BSET.B #6, @H'FFFC MOV.B #75, @H'FFF0 BSET.B #0, @H'FFF4
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Table 5-2 Interrupts, Vectors, and Priorities
Assignable Priority Levels (Initial Level) 8 (8) 7 to 0 (0) 7 to 0 (0) 7 to 0 (0) Priority among Interrupts on Same Level* High
Interrupt NMI IRQ0 IRQ1 16-Bit FRT1 ICI OCIA OCIB FOVI 16-Bit ICI FRT2 OCIA OCIB FOVI 16-Bit ICI FRT3 OCIA OCIB FOVI 8-Bit CMIA timer CMIB OVI SCI ERI RXI TXI A/D ADI converter
IPR Bits -- IPRA bits 6 to 4 IPRA bits 2 to 0 IPRB bits 6 to 4
Priority within Module -- -- -- 3 2 1 0 3 2 1 0 3 2 1 0 2 1 0 2 1 0 --
Vector Table Entry Address Minimum Maximum Mode Mode H'16 - H'17 H'2C - H'2F H'40 - H'41 H'42 - H'43 H'48 - H'49 H'4A - H'4B H'4C - H'4D H'4E - H'4F H'50 - H'51 H'52 - H'53 H'54 - H'55 H'56 - H'57 H'58 - H'59 H'5A - H'5B H'5C - H'5D H'5E - H'5F H'60 - H'61 H'62 - H'63 H'64 - H'65 H'68 - H'69 H'6A - H'6B H'6C - H'6D H'70 - H'71 H'80 - H'83 H'84 - H'87 H'90 - H'93 H'94 - H'97 H'98 - H'9B H'9C - H'9F H'A0 - H'A3 H'A4 - H'A7 H'A8 - H'AB H'AC - H'AF H'B0 - H'B3 H'B4 - H'B7 H'B8 - H'BB H'BC - H'BF H'C0 - H'C3 H'C4 - H'C7 H'C8 - H'CB H'D0 - H'D3 H'D4 - H'D7 H'D8 - H'DB H'E0 - H'E3
7 to 0 (0)
IPRB bits 2 to 0
7 to 0 (0)
IPRC bits 6 to 4
7 to 0 (0) 7 to 0 (0) 7 to 0 (0)
IPRC bits 2 to 0 IPRD bits 6 to 4 IPRD bits 2 to 0
Low
* If two or more interrupts are requested simultaneously, they are handled in order of priority level, as set in registers IPRA to IPRD. If they have the same priority level because they are requested from the same on-chip supporting module, they are handled in a fixed priority order within the module. If they are requested from different modules to which the same priority level is assigned, they are handled in the order indicated in the right-hand column.
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5.3 Register Descriptions
5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) IRQ0, IRQ1, and the on-chip supporting modules are each assigned three bits in one of the four interrupt priority registers (IPRA to IPRD). These bits specify a priority level from 7 (high) to 0 (low) for interrupts from the corresponding source. The drawing below shows the configuration of the interrupt priority registers. Table 5-3 lists their assignments to interrupt sources.
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4 3 -- 0 R 0 R/W 0 R/W 0 R/W 2 1 0
Note: Bits 7 and 3 are reserved. They cannot be modified and are always read as "0."
Table 5-3 Assignment of Interrupt Priority Registers
Interrupt Request Source Bits 6 to 4 Bits 2 to 0 IRQ0 IRQ1 16-Bit FRT1 16-Bit FRT2 16-Bit FRT3 8-Bit timer SCI A/D converter
Register IPRA IPRB IPRC IPRD
Address H'FFF0 H'FFF1 H'FFF2 H'FFF3
As table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt sources. A user program can assign desired levels to these interrupt sources by writing "000" in bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or "111" to set priority level 7. A reset clears registers IPRA to IPRD to H'00, so all interrupts except NMI are initially masked.
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When the interrupt controller receives one or more interrupt requests, it selects the request with the highest priority and compares its priority level with the interrupt mask level set in bits I2 to I0 in the CPU status register. If the priority level is higher than the mask level, the interrupt controller passes the interrupt request to the CPU (or starts the data transfer controller). If the priority level is lower than the mask level, the interrupt controller leaves the interrupt request pending until the interrupt mask is altered to a lower level or the interrupt priority is raised. Similarly, if it receives two interrupt requests with the same priority level, the interrupt controller determines their priority as explained in table 5-2 and leaves the interrupt request with the lower priority pending. 5.3.2 Timing of Priority Setting The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies an instruction priority register, the new priority does not take effect until after the next instruction has been executed.
5.4 Interrupt Handling Sequence
5.4.1 Interrupt Handling Flow The interrupt-handling sequence follows the flowchart in figure 5-2. Note that address error, trace exception, and NMI requests bypass the interrupt controller's priority decision logic and are routed directly to the CPU. 1. Interrupt requests are generated by one or more on-chip supporting modules or external interrupt sources. 2. The interrupt controller checks the interrupt priorities set in IPRA to IPRD and selects the interrupt with the highest priority. Interrupts with lower priorities remain pending. Among interrupts with the same priority level, the interrupt controller determines priority as explained in table 5-2. 3. The interrupt controller compares the priority level of the selected interrupt request with the mask level in the CPU status register (bits I2 to I0). If the priority level is equal to or less than the mask level, the interrupt request remains pending. If the priority level is higher than the mask level, the interrupt controller accepts the interrupt request and proceeds to the next step. 4. The interrupt controller checks the corresponding bit (if any) in the data transfer enable registers (DTEA to DTED). If this bit is set to "1," the data transfer controller is started. Otherwise, the CPU interrupt exception-handling sequence is started. When the data transfer controller is started, the interrupt request is cleared (except for interrupt requests from the serial communication interface, which are cleared by writing to the TDR or reading the RDR).
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If the data transfer enable bit is cleared to "0" (or is nonexistent), the sequence proceeds as follows. For the case in which the data transfer controller is started, see section 6, "Data Transfer Controller." 5. After the CPU has finished executing the current instruction, the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3 (a) or (b). The program counter value saved on the stack is the address of the next instruction to be executed. 6. The T (Trace) bit of the status register is cleared to "0," and the priority level of the interrupt is copied to bits I2 to I0, thus masking further interrupts unless they have a higher priority level. When an NMI is accepted, the interrupt mask level in bits I2 to I0 is set to 7. 7. The interrupt controller generates the vector address of the interrupt, and the entry at this address in the exception vector table is read to obtain the starting address of the user-coded interrupt handling routine. In step 7, the same difference between the minimum and maximum modes exists as in the reset handling sequence. In the minimum mode, one word is copied from the vector table to the program counter, then the interrupt-handling routine starts executing from the address indicated in the program counter. In the maximum mode, two words are read. The lower byte of the first word is copied to the code page register. The second word is copied to the program counter. The interrupt-handling routine starts executing from the address indicated in the code page register and program counter.
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Program execution state N Interrupt requested? Address error? Y N N Trace? NMI? Y Y N N Level-7 interrupt? Y Level-6 interrupt? Y Mask level in SR 6? Y Mask level in SR 5? Y Level-1 interrupt? Y N N Mask level in SR = 0? Y N N N Y
Interrupt remains pending Data transfer enabled? N Exception-handling sequence Save PC Y Start DTC Read DTC vector Read transfer mode Read source address Read data Maximum mode? N Y Save PC Source address increment mode? N Save SR Write source address Read destination address Write data N Trace Destination address increment mode? Address error? Y N Update mask level N Y Y
Increment source address (+1 or +2)
Clear T bit
Increment source address (+1 or +2) Write destination address
Read DTCR Vectoring DTCR-1 DTCR Write DTCR To user-coded exception-handling routine Y DTCR = 0? N
Figure 5-2 Interrupt Handling Flowchart
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5.4.2 Stack Status after Interrupt Handling Sequence Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence.
Address
Address
2m - 4 2m - 3 2m - 2 2m - 1 2m Stack area SP
2m - 4 2m - 3 2m - 2 2m - 1 2m
Upper 8 bits of SR Lower 8 bits of SR Upper 8 bits of PC Lower 8 bits of PC
SP
(Before) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address (e.g 2m).
(After)
Figure 5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode)
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Address 2m - 6 2m - 5 2m - 4 2m - 3 2m - 2 2m - 1 2m Stack area SP
Address 2m - 6 2m - 5 2m - 4 2m - 3 2m - 2 2m - 1 2m Upper 8 bits of SR Lower 8 bits of SR Don't care CP Upper 8 bits of PC Lower 8 bits of PC SP
(Before) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address (e.g 2m).
(After)
Figure 5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) 5.4.3 Timing of Interrupt Exception-Handling Sequence Figure 5-4 shows the timing of the exception-handling sequence for an interrupt when the program area and stack area are both in on-chip memory and the user-coded interrupt handling routine starts at an even address.
5.5 Interrupts During Operation of the Data Transfer Controller
If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the data transfer cycle has been completed and the next instruction has been executed. This is true even if the interrupt is an NMI. An example is shown below. Program flow (Example)
DTC interrupt request
ADD.W MOV.W ADD.W
R2, R0 R0, @H'FF00 @H' FF02,R0
Data transfer cycle request
NMI interrupt
After data transfer cycle, CPU executes next instruction before starting exception handling
To NMI exception handling sequence
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o
Interrupt address bus (1) SP - 2 SP - 4 (1) Vector address (3)
(1)
NMI, IRQ0 IRQ 1
Interrupt data bus (16 bits) (2) (2) PC SR Vector
(2)
(4)
Figure 5-4 Interrupt Sequence (Minimum Mode, On-Chip Memory)
Priority level decision and wait for end of current instruction (2) Instruction code Internal processing cycle Stack access Prefetch first Start instruction Interrupt accepted instruction of execution interrupthandling routine (3) Starting address of interrupt-handling routine
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Interrupt reset signal
Interrupt write signal
(1) Instruction prefetch address
(4) First instruction of interrupt-handling routine
Note: This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the interrupt-handling routine starts at an even address.
o
Internal address bus
SP - 2 address address + 1 address + 2 address + 3 SP - 1 SP - 4 SP - 3 SP - 6 SP - 5 Vector Vector Vector Vector (3)
(1)
(1)
NMI, IRQ 0 IRQ1
Internal data bus (16 bits)
PC H PC L CP SR H SR L Vector Vector Vector don't care don't care
(2)
(2)
(4)
Internal Read signal
Internal Write signal
Figure 5-5 Interrupt Sequence (Maximum Mode, External Memory)
Stack access Interrupt vector Prefetch first instruction of interrupt-handling routine
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Priority level decision Internal and wait for processing end of cycle current instruction
Start instruction execution
(1) Instruction prefetch address
(2) Instruction code
(3) Starting address of interrupt-handling routine
(4) First instruction of interrupt-handling routine
Note: This timing chart applies to the maximum mode when the program and stack areas are both in external memory. Instruction execution starts after interrupt vector fetch and 4-byte (4 bys cycles) instruction prefetch has been done.
5.6 Interrupt Response Time
Table 5-4 indicates the number of states that may elapse between the generation of an interrupt request and the execution of the first instruction of the interrupt-handling routine, assuming that the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is performed to on-chip memory areas, fastest interrupt service can be obtained by placing the program in on-chip ROM and the stack in on-chip RAM. Table 5-4 Number of States before Interrupt Service
Number of States Minimum Mode Maximum Mode 2 states
No. 1 2
Reason for Wait Interrupt priority decision and comparison with mask level in CPU status register Maximum number of Instruction is in on-chip states to completion memory of current instruction Instruction is in external memory
Saving of PC and SR or PC, CP, and SR and instruction prefetch Stack is in Instruction is in on-chip on-chip RAM memory Instruction is in external Total memory Stack is in Instruction is in on-chip external RAM memory Instruction is in external memory
3
x (x = 38 for LDM instruction specifying all registers) y (y = 74 + 16m for LDM instruction specifying all registers) Stack is in on-chip RAM 16 21 Stack is in external memory 28 + 6m 41 + 10m 18 + x (56) 18 + y (92 + 16m) 30 + 6m + x (68 + 6m) 30 + 6m + y (104 + 22m) 23 + x (61) 23 + y (97 + 16m) 43 + 10m + x (81 + 10m) 43 + 10m + y (117 + 26m)
Note: m: Number of wait states inserted in external memory access. Values in parentheses are for the LDM instruction.
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Section 6 Data Transfer Controller
6.1 Overview
The H8/532 chip includes a data transfer controller (DTC) that can be started by designated interrupts to transfer data from a source address to a destination address located in page 0. These addresses include in particular the registers of the on-chip supporting modules and I/O ports. Typical uses of the DTC are to change the setting of a control register of an on-chip supporting module in response to an interrupt from that module, or to transfer data from memory to an I/O port or the serial communication interface. Once set up, the transfer is interrupt-driven, so it proceeds independently of program execution, although program execution temporarily stops while each byte or word is being transferred. 6.1.1 Features The main features of the DTC are listed below. * The source address and destination address can be set anywhere in the 64k-byte address space of page 0. * The DTC can be programmed to transfer one byte or one word of data per interrupt. * The DTC can be programmed to increment the source address and/or destination address after each byte or word is transferred. * After transferring a designated number of bytes or words, the DTC generates a CPU interrupt with the vector of the interrupt source that started the DTC. * This designated data transfer count can be set from 1 to 65,536 bytes or words. 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the DTC. The four DTC control registers (DTMR, DTSR, DTDR, and DTCR) are invisible to the CPU, but corresponding information is kept in a register information table in memory. A separate table is maintained for each DTC interrupt type. When an interrupt requests DTC service, the DTC loads its control registers from the table in memory, transfers the byte or word of data, and writes any altered register information back to memory.
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Internal data bus
DTC request RAM Interrupt controller IRQ 0 IRQ 1 DTEA DTEB DTEC DTED DTMR DTSR DTDR DTCR DTC Register information table 0 Register information table 1
DTMR: DT Mode Register DTSR: DT Source Address Register DTDR: DT Destination Address Register DTCR: DT Count Register DTEA to DTED: DT Enable Register A to D
Figure 6-1 Block Diagram of Data Transfer Controller 6.1.3 Register Configuration The four DTC control registers are listed in table 6-1. These registers are not located in the address space and cannot be written or read by the CPU. To set information in these registers, a program must write the information in a table in memory from which it will be loaded by the DTC. Table 6-1 Internal Control Registers of the DTC
Name Data transfer mode register Data transfer source address register Data transfer destination address register Data transfer count register Abbreviation DTMR DTSR DTDR DTCR Read/Write Disabled Disabled Disabled Disabled
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Starting of the DTC is controlled by the four data transfer enable registers, which are located in high addresses in page 0. Table 6-2 lists these registers. Table 6-2 Data Transfer Enable Registers
Name Data transfer enable register Abbreviation DTEA DTEB DTEC DTED Read/Write R/W R/W R/W R/W Address H'FFF4 H'FFF5 H'FFF6 H'FFF7 Initial Value H'00 H'00 H'00 H'00
A B C D
6.2 Register Descriptions
6.2.1 Data Transfer Mode Register (DTMR)
Bit 15 Sz Read/Write -- 14 SI -- 13 DI -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- --
The data transfer mode register is a 16-bit register, the first three bits of which designate the data size and specify whether to increment the source and destination addresses. Bit 15--Sz (Size): This bit designates the size of the data transferred.
Bit 15 Sz Description 0 Byte transfer 1 Word transfer* (two bytes at a time) * For word transfer, the source and destination addresses must be even addresses.
Bit 14--SI (Source Increment): This bit specifies whether to increment to source address.
Bit 14 SI 0 1
Description Source address is not incremented. 1) If Sz = 0: Source address is incremented by +1 after each data transfer. 2) If Sz = 1: Source address is incremented by +2 after each data transfer.
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Bit 13--DI (Destination Increment): This bit specifies whether to increment to destination address.
Bit 13 DI 0 1
Description Destination address is not incremented. 1) If Sz = 0: Destination address is incremented by +1 after each data transfer. 2) If Sz = 1: Destination address is incremented by +2 after each data transfer.
Bits 12 to 0--Reserved Bits: These bits are reserved. 6.2.2 Data Transfer Source Address Register (DTSR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
The data transfer source register is a 16-bit register that designates the data transfer source address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.3 Data Transfer Destination Register (DTDR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
The data transfer destination register is a 16-bit register that designates the data transfer destination address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.4 Data Transfer Count Register (DTCR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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The data transfer count register is a 16-bit register that counts the number of bytes or words of data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value of 0 designates an initial count of 65,536. The data transfer count register is decremented automatically after each byte or word is transferred. When its value reaches 0, indicating that the designated number of bytes or words have been transferred, a CPU interrupt is generated with the vector of the interrupt that requested the data transfer. 6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) These four registers designate whether an interrupt starts the DTC. The bits in these registers are assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, FOVI, OVI, and ERI interrupts, which cannot request data transfers.
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Table 6-3 Assignment of Data Transfer Enable Registers
Interrupt Source Register Module Bits 7 to 4 7 6 DTEA IRQ0 -- -- DTEB DTEC DTED 16-Bit FRT1 16-Bit FRT3 SCI -- -- -- Interrupt Source Module Bits 3 to 0 3 2 IRQ1 -- -- 16-Bit FRT2 8-Bit Timer A/D converter -- -- --
5 --
4 IRQ0 ICI ICI --
1 --
0 IRQ1 ICI
OCIB OCIA OCIB OCIA TXI RXI
OCIB OCIA -- --
CMIB CMIA -- ADI
Note: Bits marked "--" should always be cleared to "0."
If the bit for a certain interrupt is set to "1," that interrupt is regarded as a request for DTC service. If the bit is cleared to "0," the interrupt is regarded as a CPU interrupt request. Only the 16 interrupts indicated in table 6-3 can request DTC service. DTE bits not assigned to any interrupt (indicated by "--" in table 6-3) should be left cleared to "0."
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* Note on Timing of DTE Modifications: The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies a data transfer enable register, the new setting does not take effect until the third state after that instruction has been executed.
6.3 Data Transfer Operation
6.3.1 Data Transfer Cycle When started by an interrupt, the DTC executes the following data transfer cycle: 1. From the DTC vector table, the DTC reads the address at which the register information table for that interrupt is located in memory. 2. The DTC loads the data transfer mode register and source address register from this table and reads the data (one byte or word) from the source address. 3. If so specified in the mode register, the DTC increments the source address register and writes the new source address back to the table in memory. 4. The DTC loads the data transfer destination address register and writes the byte or word of data to the destination address. 5. If so specified in the mode register, the DTC increments the destination address register and writes the new destination address back to the table in memory. 6. The DTC loads the data transfer count register from the table in memory, decrements the data count, and writes the new count back to memory. 7. If the data transfer count is now 0, the DTC generates a CPU interrupt. The interrupt vector is the vector of the interrupt type that started the DTC. At an appropriate point during this procedure the DTC also clears the interrupt request by clearing the corresponding flag bit in the status register of the on-chip supporting module to "0." (For IRQ0 or IRQ1, the DTC clears an internal latch.) But the DTC does not clear the data transfer enable bit in the data transfer enable register. This action, if necessary, must be taken by the user-coded interrupt-handling routine invoked at the end of the transfer. The data transfer cycle is shown in a flowchart in figure 6-2. For the steps from the occurrence of the interrupt up to the start of the data transfer cycle, see section 5.4.1, "Interrupt Handling Flow."
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INT N
Interrupt CPU
DTC interrupt? DTC Y
Save PC and SR Read DTC vector Read vector Read transfer mode Read source address Read data Y Start executing interrupt-handling routine at that address. Read address from vector table
Source address increment mode? N
Increment source address (+1 or +2) Write source address
Read destination address Write data
Destination address increment mode? N
Y
Increment destination address (+1 or +2) Write destination address
Read DTCR DTCR DTCR Write DTCR Y DTCR = 0? N DTC END
Figure 6-2 Flowchart of Data Transfer Cycle
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6.3.2 DTC Vector Table The DTC vector table is located immediately following the exception vector table at the beginning of page 0 in memory. For each interrupt that can request DTC service, the DTC vector table provides a pointer to an address in memory where the table of DTC control register information for that interrupt is stored. The register information tables can be placed in any available locations in page 0.
Vector table RAM
DTMR0 Register information table 0 DTSR0 DTDR0 DTCR0
Exception vector table
TA0
DTMR1 TA0 TA1 TA1 DTC vector table Register information table 1 DTSR1 DTDR1 DTCR1
Note: TA0, TA1, ...: Addresses of DTC register information tables in memory.
ote: TA 0 , TA1,... : Addresses of DTC register information tables in memory.
In the normal case the register information tables are placed on a RAM. If the software does not need to modify the register information (addresses are fixed and transfer count is 1), it can be placed on ROM.
Figure 6-3 DTC Vector Table In minimum mode, each entry in the DTC vector table consists of two bytes, pointing to an address in page 0. In maximum mode, for compatibility reasons, each DTC vector table entry consists of four bytes but the first two bytes are ignored; the last two bytes point to an address which is implicitly assumed to be in page 0, regardless of the current page specifications. Figure 6-4 shows one DTC vector table entry in minimum and maximum mode.
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DTC vector table Address m Address (H)
RAM
DTC vector table Address
Register information
Don't care
2m*
m+1
Address (L)
Don't care
2 m + 1*
Address (H)
2m+2
Address (L)
2m+3
(1) Minimum mode * Address 2m and 2m + 1 are not accessed at vector read.
(2) Maximum mode
Figure 6-4 DTC Vector Table Entry Table 6-4 lists the addresses of the entries in the DTC vector table for each interrupt. Table 6-4 Addresses of DTC Vectors
Interrupt IRQ0 IRQ1 16-Bit free-running timer 1 (FRT1) 16-Bit free-running timer 2 (FRT2) 16-Bit free-running timer 3 (FRT3) Address of DTC Vector Minimum Mode Maximum Mode H'0080 - H'0081 H'0100 - H'0103 H'0082 - H'0083 H'0104 - H'0107 H'0088 - H'0089 H'0110 - H'0113 H'008A - H'008B H'0114 - H'0117 H'008C - H'008D H'0118 - H'011B -- -- H'0090 - H'0091 H'0120 - H'0123 H'0092 - H'0093 H'0124 - H'0127 H'0094 - H'0095 H'0128 - H'012B -- -- H'0098 - H'0099 H'0130 - H'0133 H'009A - H'009B H'0134 - H'0137 H'009C - H'009D H'0138 - H'013B -- --
ICI OCIA OCIB FOVI ICI OCIA OCIB FOVI ICI OCIA OCIB FOVI
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Table 6-4 Addresses of DTC Vectors (cont)
Address of DTC Vector Minimum Mode Maximum Mode H'00A0 - H'00A1 H'0140 - H'0143 H'00A2 - H'00A3 H'0144 - H'0147 -- -- -- -- H'00AA - H'00AB H'0154 - H'0157 H'00AC - H'00AD H'0158 - H'015B H'00B0 - H'00B1 H'0160 - H'0163
Interrupt 8-Bit timer Serial communication interface A/D converter
CMIA CMIB OVI ERI RXI TXI ADI
6.3.3 Location of Register Information in Memory For each interrupt, the DTC control register information is stored in four consecutive words in memory in the order shown in figure 6-5.
DTC vector table RAM
DTMR TA + 2 TA TA + 4 TA + 6 DTSR DTDR DTCR 8 Bits 8 Bits
Mode register Source address register Destination address register
Count register
Figure 6-5 Order of Register Information 6.3.4 Length of Data Transfer Cycle Table 6-5 lists the number of states required per data transfer, assuming that the DTC control register information is stored in on-chip RAM. This is the number of states required for loading and saving the DTC control registers and transferring one byte or word of data. Two cases are considered: a transfer between on-chip RAM and a register belonging to an I/O port or on-chip supporting module (i.e., a register in the register field from addresses H'FF80 to H'FFFF); and a transfer between such a register and external RAM.
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Table 6-5 Number of States per Data Transfer
Increment Mode Source Destina(SI) tion (DI) 0 0 0 1 1 0 1 1 On-Chip RAM Module or I/O Register Byte Transfer Word Transfer 31 34 33 36 33 36 35 38 External RAM Module or I/O Register Byte Transfer Word Transfer 32 38 34 40 34 40 36 42
Note: Numbers in the table are the number of states.
The values in table 6-5 are calculated from the formula: N = 26 + 2 x SI + 2 x DI + MS + MD Where MS and MD have the following meanings: MS: Number of states for reading source data MD: Number of states for writing destination data The values of MS and MD depend on the data location as follows: Byte or word data in on-chip RAM: 2 states Byte data in external RAM or register field: 3 states Word data in external RAM or register field: 6 states If the DTC control register information is stored in external RAM, 20 + 4 x SI + 4 x DI must be added to the values in table 6-5. The values given above do not include the time between the occurrence of the interrupt request and the starting of the DTC. This time includes two states for the interrupt controller to check priority and a variable wait until the end of the current CPU instruction. At maximum, this time equals the sum of the values indicated for items No. 1 and 2 in table 6-6. If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is executed is the value given for item No. 3 in table 6-6.
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Table 6-6 Number of States before Interrupt Service
Number of States Minimum Mode Maximum Mode 2 states 38 (LDM instruction specifying all registers) 74 + 16m (LDM instruction specifying all registers) 16 21 28 + 6m 41 + 10m
No. Reason for Wait 1 Interrupt priority decision and comparison with mask level in CPU status register 2 Maximum number of Instruction is in on-chip states to completion memory of current instruction Instruction is in external memory 3 Saving of PC and SR Stack is in on-chip RAM or PC, CP, and SR and instruction prefetch Stack is in external memory
m: Number of wait states inserted in external memory access
6.4 Procedure for Using the DTC
A program that uses the DTC to transfer data must do the following: 1. Set the appropriate DTMR, DTSR, DTDR, and DTCR register information in the memory location indicated in the DTC vector table. 2. Set the data transfer enable bit of the pertinent interrupt to "1," and set the priority of the interrupt source (in the interrupt priority register) and the interrupt mask level (in the CPU status register) so that the interrupt can be accepted. 3. Set the interrupt enable bit in the control register for the interrupt source. (For IRQ0 and IRQ1, the control register is the port 1 control register, P1CR.) Following these preparations, the DTC will be started each time the interrupt occurs. When the number of bytes or words designated by the DTCR value have been transferred, after transferring the last byte or word, the DTC generates a CPU interrupt. The user-coded interrupt-handling routine must take action to prepare for or disable further DTC data transfer: by readjusting the data transfer count, for example, or clearing the interrupt enable bit. If no action is taken, the next interrupt of the same type will start the DTC with an initial data transfer count of 65,536.
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6.5 Example
Purpose: To receive 128 bytes of serial data via the serial communication interface. Conditions: * * * * Operating mode: Minimum mode Received data are to be stored in consecutive addresses starting at H'FC00. DTC control register information for the RXI interrupt is stored at addresses H'FB80 to H'FB87. Accordingly, the DTC vector table contains H'FB at address H'00AA and H'80 at address H'00AB. * The desired interrupt mask level in the CPU status register is 4, and the desired SCI interrupt priority level is 5. Procedure 1. The user program sets DTC control register information in addresses H'FB80 to H'FB87 as shown in table 6-7. Table 6-7 DTC Control Register Information Set in RAM
Address H'FB80 H'FB82 H'FB84 H'FB86 Register DTMR DTSR DTDR DTCR Description Byte transfer Source address fixed Increment destination address Address of SCI receive data register Address H'FC00 Number of bytes to be received: 128 Value Set H'2000 H'FFDD H'FC00 H'0080
2. The program sets the RI (SCI Receive Interrupt) bit in the data transfer enable register (bit 5 of register DTED) to "1." 3. The program sets the interrupt mask in the CPU status register to 4, and the SCI interrupt priority in bits 6 to 4 of interrupt priority register IPRD to 5. 4. The program sets the SCI to the appropriate receive mode, and sets the receive interrupt enable (RIE) bit in the serial control register (SCR) to "1" to enable receive interrupts. 5. Thereafter, each time the SCI receives one byte of data, it requests an RXI interrupt, which the interrupt controller directs toward the DTC. The DTC transfers the byte from the SCI's receive data register (RDR) into RAM, and clears the interrupt request before ending.
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6. When 128 bytes have been transferred (DTCR = 0), the DTC generates a CPU interrupt. The interrupt type is RXI. 7. The user-coded RXI interrupt-handling routine processes the received data and disables further data transfer (by clearing the RIE bit, for example). Figure 6-6 shows the DTC vector table and data in RAM for this example.
DTC vector table
Address H'FB80 H'FB81
RAM H'20 Mode H'00 H'FF Source address H'DD H'FC Destination address H'00 H'00 Counter
Address H'00AA H'00AB H'FB H'80
H'FB87
H'80
H'FC00
Receive data 1 Receive data 2
Transferred by DTC H'FC7F Receive data 128
RDR SCI
Figure 6-6 Use of DTC to Receive Data via Serial Communication Interface
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Section 7 Wait-State Controller
7.1 Overview
To simplify interfacing to low-speed external devices, the H8/532 has an on-chip wait-state controller (WSC) that can insert wait states (TW) to prolong bus cycles. The wait-state function can be used in CPU and DTC access cycles to external addresses. It is not used in access to on-chip supporting modules. The TW states are inserted between the T2 state and T3 state in the bus cycle. The number of wait states can be selected by a value set in the waitstate control register (WCR), or by holding the WAIT pin Low for the required interval. 7.1.1 Features The main features of the wait-state controller are: * Selection of three operating modes Programmable wait mode, pin wait mode, or pin auto-wait mode * 0, 1, 2, or 3 wait states can be inserted. And in the pin wait mode, 4 or more states can be inserted by holding the WAIT pin Low.
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7.1.2 Block Diagram Figure 7-1 shows a block diagram of the wait-state controller.
Internal data bus
WCR -- -- -- -- WMS1 WMS0 WC1 WC0
Wait counter
WAIT request
Control logic
WAIT input
WCR: Wait-state Control Register WMS1, 0: Wait Mode Select 1, 0 WC1, 0: Wait Count 1, 0
Figure 7-1 Block Diagram of Wait-State Controller 7.1.3 Register Configuration The wait-state controller has one control register: the wait-state control register described in table 7-1. Table 7-1 Register Configuration
Name Wait-state control register Abbreviation WCR Read/Write R/W Initial Value H'F3 Address H'FFF8
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7.2 Wait-State Control Register
The wait-state control register (WCR) is an 8-bit register that specifies the wait mode and the number of wait states to be inserted. A reset initializes the WCR to specify the programmable wait mode with three wait states. The WCR is not initialized in the software standby mode.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W
Bits 7 to 4--Reserved: These bits cannot be modified and are always read as "1." Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1 and WMS0): These bits select the wait mode as shown below.
Bit 3 WMS1 0 0 1 1 Bit 2 WMS0 0 1 0 1
Description Programmable wait mode (Initial value) No wait states are inserted, regardless of the wait count. Pin wait mode Pin auto-wait mode
Bits 1 and 0--Wait Count (WC1 and WC0): These bits specify the number of wait states to be inserted. Wait states are inserted only in bus cycles in which the CPU or DTC accesses an external address.
Bit 1 WC1 0 0 1 1 Bit 0 WC0 0 1 0 1
Description No wait states are inserted, except in pin wait mode. 1 Wait state in inserted. 2 Wait states are inserted. 3 Wait states are inserted. (Initial value)
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7.3 Operation in Each Wait Mode
Table 7-2 summarizes the operation of the three wait modes. Table 7-2 Wait Modes
WAIT Insertion Pin Function Conditions Disabled Inserted on access to an off-chip address Number of Wait States Inserted 1 to 3 wait states are inserted, as specified by bits WC0 and WC1.
Mode Programmable wait mode WMS1 = "0" WMS0 = "0" Pin wait mode WMS1 = "1" WMS0 = "0" Pin auto-wait mode WMS1 = "1" WMS0 = "1"
Enabled
Enabled
Inserted on access to 0 to 3 wait states are inserted, as an off-chip address specified by bits WC0 and WC1, plus additional wait states while the WAIT pin is held Low. Inserted on access to 1 to 3 wait states are inserted, as an off-chip address if specified by bits WC0 and WC1. the WAIT pin is Low
7.3.1 Programmable Wait Mode The programmable wait mode is selected when WMS1 = "0" and WMS0 = "0." Whenever the CPU or DTC accesses an off-chip address, the number of wait states set in bits WC1 and WC0 are inserted. The WAIT pin is not used for wait control; it is available as an I/O pin.
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Figure 7-2 shows the timing of the operation in this mode when the wait count is 1 (WC1 = "0," WC0 = "1").
T2 state or T3 o
T1
T2
TW
T3
A19 -A 0
Off-chip address
RD, AS, DS (Read) Read data D7 -D0 Read data
WR, DS (Write) D7 -D0 Write data
Figure 7-2 Programmable Wait Mode
7.3.2 Pin Wait Mode The pin wait mode is selected when WMS1 = "1" and WMS0 = "0." In this mode the WAIT function of the P14 /WAIT pin is used automatically. The number of wait states indicated by bits WC1 and WC0 are inserted into any bus cycle in which the CPU or DTC accesses an off-chip address. In addition, wait states continue to be inserted as long as the WAIT pin is held low. In particular, if the wait count is 0 but the WAIT pin is Low at the rising edge of the o clock in the T2 state, wait states are inserted until the WAIT pin goes High. This mode is useful for inserting four or more wait states, or when different external devices require different numbers of wait states.
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Figure 7-3 shows the timing of the operation in this mode when the wait count is 1 (WC1 = "0," WC0 = "1") and the WAIT pin is held Low to insert one additional wait state.
Wait count TW WAIT pin TW
T1
T2
T3
o
*
*
WAIT pin
A19 -A 0 RD, AS, DS (Read)
Off-chip address
Read data D7 -D0 WR, DS (Write)
D7 -D0
Write data
* The arrowheads indicate the times at which the WAIT pin is sampled.
Figure 7-3 Pin Wait Mode
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7.3.3 Pin Auto-Wait Mode The pin auto-wait mode is selected when WMS1 = "1" and WMS0 = "1." In this mode the WAIT function of the P14 /WAIT pin is used automatically. In this mode, the number of wait states indicated by bits WC1 and WC0 are inserted, but only if there is a Low input at the WAIT pin. Figure 7-4 shows the timing of this operation when the wait count is 1. In the pin auto-wait mode, the WAIT pin is sampled only once, on the falling edge of the o clock in the T2 state. If the WAIT pin is Low at this time, the wait-state controller inserts the number of wait states indicated by bits WC1 and WC0. The WAIT pin is not sampled during the Tw and T3 states, so no additional wait states are inserted even if the WAIT pin continues to be held Low. This mode offers a simple way to interface a low-speed device: the wait states can be inserted by routing an address decode signal to the WAIT pin.
T1 T2 T3 T1 T2 TW T3
o
*
*
WAIT
A19 -A 0
External address
External address
RD, AS, DS (Read) Read data D7 -D0 Read data
WR, DS (Write)
D7 -D0
Write data
Write data
* The arrowheads indicate the times at which the WAIT pin is sampled.
Figure 7-4 Pin Auto-Wait Mode
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Section 8 Clock Pulse Generator
8.1 Overview
The H8/532 chip has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (o) clock divider, an E clock divider, and a group of prescalers. The prescalers generate clock signals for the on-chip supporting modules. 8.1.1 Block Diagram
CPG
Prescaler Divider /2 Divider /8
XTAL EXTAL
Oscillator circuit
o
E
o/2 to o/4096
Figure 8-1 Block Diagram of Clock Pulse Generator
8.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. Alternatively, an external clock signal can be applied to the EXTAL pin. Connecting an External Crystal (1) Circuit Configuration: An external crystal can be connected as in the example in figure 8-2. An AT-cut parallel resonating crystal should be used.
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CL1 EXTAL
XTAL CL2 CL1 =C L2 =10 to 22pF
Figure 8-2 Connection of Crystal Oscillator (Example) (2) Crystal Oscillator: The external crystal should have the characteristics listed in table 8-1.
CL L XTAL RS EXTAL
C0 AT-cut parallel resonating crystal
Figure 8-3 Crystal Oscillator Equivalent Circuit Table 8-1 External Crystal Parameters
Frequency (MHz) Rs max () C0 (pF) 2 4 500 120 7pF max 8 60 12 40 16 30 20 20
(3) Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 8-4. When the board is designed, the crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins.
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Not allowed
Signal A
Signal B
H8/532
CL2 XTAL
EXTAL CL1
Figure 8-4 Notes on Board Design around External Crystal Input of External Clock Signal (1) Circuit Configuration: An external clock signal can be input at the EXTAL and XTAL pins as shown in the example in figure 8-5.
EXTAL 74HC04 XTAL External clock input
Figure 8-5 External Clock Input (Example) Note: When using make ROM, an external clock can be input at the EXTAL pin while leaving the XTAL pin open. Also when using ZTAT, an external clock under 16 MHz can be input at the EXTAL pin while leaving the XTAL pin open.
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(2) External Clock Input
Frequency Duty factor Double the system clock (o) frequency 45% to 55%
8.3 System Clock Divider
The system clock divider divides the crystal oscillator or external clock frequency (fosc) by 2 to create the o clock. An E clock signal is created by dividing the o clock by 8. The E clock is used for interfacing to E clock based devices. Figure 8-6 shows the phase relationship of the E clock to the o clock.
o
E E
Figure 8-6 Phase Relationship of o Clock and E Clock
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Section 9 I/O Ports
9.1 Overview
The H8/532 has nine ports. Ports 1, 3, 4, 5, 7, and 9 are eight-bit input/output ports. Port 2 is a five-bit input/output port. Port 6 is a four-bit input/output port. Port 8 is an eight-bit input-only port. Table 9-1 summarizes the functions of each port. Input and output are memory-mapped. The CPU views each port as a data register (DR) located in the register field at the high end of page 0 of the address space. Each port (except port 8) also has a data direction register (DDR) which determines which pins are used for input and which for output. Port 1 has an additional control register (P1CR) for enabling and disabling IRQ0 and IRQ1 and setting other controls. To read data from an I/O port, the CPU selects input in the data direction register and reads the data register. This causes the input logic level at the pin to be placed directly on the internal data bus. There is no intervening input latch. To send data to an output port, the CPU selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. The latch output drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. As table 9-1 indicates, all of the I/O port pins have dual functions. For example, pin 7 of port 1 can be used either as a general-purpose I/O pin (P17), or for output of the TMO signal from the on-chip 8-bit timer. The function is determined by the MCU operating mode, or by a value set in a control register. Outputs from ports 1 to 6 can drive one TTL load and a 90pF capacitive load. Outputs from ports 7 and 9 can drive one TTL load and a 30pF capacitive load. Outputs from ports 1 to 7 and 9 can also drive a Darlington transistor pair. Outputs from port 4 can drive a light-emitting diode (with 10mA current sink). Ports 5 and 6 have built-in MOS pullups for each input. Port 7 has Schmitt inputs. Schematic diagrams of the I/O port circuits are shown in appendix C.
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Table 9-1 Input/Output Port Summary
Expanded Modes Mode 1 Mode 2 Mode 3 Mode 4 These input/output pins double as and inputs and as IRQ0 and IRQ1 input and output pin (TMO) for the 8-bit timer. These pins function as WAIT, BREQ, and BACK when necessary controlregister bits are set to "1." These pins function as input pins or as clock (E, o) output pins, depending on the data direction register setting. Bus control signal outputs (WR, RD, DS, R/W, AS) Single-Chip Mode (Mode 7)
Port Description Pins Port 1 8-Bit input/output P17 / TMO P16 / IRQ1 P15 / IRQ0 P14 / WAIT P13 / BREQ P12 / BACK P11 / E P10 / o Port 2 5-Bit input/output P24 / WR port P23 / RD P22 / DS P21 / R/W P20 / AS Port 3 8-Bit input/output P37 - P30 / port D7 - D0 Port 4 8-Bit input/output P47 - P40 / port A7 - A0 Can drive a LED Port 5 8-Bit input/output P57 - P50 / port A15 - A8 Built-in input pull-up (MOS) Port 6 4-Bit input/output P63 -P60 / port A19 - A16 Built-in input pull-up (MOS)
Input/output port
Input/output port
Data bus (D7 - D0) Low address bits (A7 - A0)
Input/output port Input/output port High address bus if DDR is set to "1" Page address bus if DDR is set to "1," input port if DDR is set to "0" Input/output port
High High High address address address bus bus if bus (A15 - DDR is (A15 - A8) set to "1" A8) Input/output port Page address bus (A19 - A16)
Input/output port
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Table 9-1 Input/Output Port Summary (cont)
Expanded Modes Single-Chip Mode Mode 1 Mode 2 Mode 3 Mode 4 (Mode 7) Input/output for free-running timers 1, 2 and 3 (FTI1 to FTI3, FTCI1 to FTCI3, FTOB1 to FTOB3, FTOA1),input for 8-bit timer input (TMCI, TMRI), and 8-bit input/output port (P77 to P70)
Pins P77 / FTOA1 P76 / FTOB3 / FTCI3 P75 / FTOB2 / FTCI2 P74 / FTOB1 / FTCI1 / P73 / FTI3 TMRI P72 / FTI2 P71 / FTI1 P70 / TMCI Port 8 8-Bit input port P80 - P87 AN7 - AN0 Port 9 8-Bit input/output P97 / SCK port P96 / RXD P95 / TXD P94 / PW3 P93 / PW2 P92 / PW1 P91 / FTOA3 P90 / FTOA2
Port Description Port 7 8-Bit input/output port (Schmitt inputs)
Analog input pins for A/D converter, and 8-bit input port Output for free-running timers 2 and 3 (FTOA2, FTOA3), PWM timer output (PW1, PW2, PW3), serial communication interface (SCI) input/output (TXD, RXD, SCK), and 8-bit input/output port
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9.2 Port 1
9.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. All pins have dual functions, except that in the single-chip mode pins 4, 3, and 2 do not have the WAIT, BREQ, and BACK functions. (because the CPU does not access an external bus.) Outputs from port 1 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair.
Pin P17 / TMO P16 / IRQ1 P15 / IRQ0 P14 / WAIT P13 / BREQ P12 / BACK P11 / E P10 / o Expanded Modes P17 (input/output) / TMO (output) P16 (input/output) / IRQ1 (input) P15 (input/output) / IRQ0 (input) P14 (input/output) / WAIT (input) P13 (input/output) / BREQ (input) P12 (input/output) / BACK (output) P11 (input) / E (output) P10 (input) / o (output) Single-Chip Mode P17 (input/output) / TMO (output) P16 (input/output) / IRQ1 (input) P15 (input/output) / IRQ0 (input) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input) / E (output) P10 (input) / o (output)
Port 1
Figure 9-1 Pin Functions of Port 1 9.2.2 Port 1 Registers Register Configuration: Table 9-2 lists the registers of port 1. Table 9-2 Port 1 Registers
Name Port 1 data direction register Port 1 data register Port 1 control register Abbreviation P1DDR P1DR P1CR Read/Write W R/W*1 R/W Initial Value H'03 Undetermined*2 H'87 Address H'FF80 H'FF82 H'FFFC
*1 Bits 1 and 0 are read-only. *2 Bits 1 and 0 are undetermined. Other bits are initialized to "0."
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1. Port 1 Data Direction Register (P1DDR)--H'FF80
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 1 W 1 W
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an output pin if the corresponding bit in P1DDR is set to "1," and as an input pin if the bit is cleared to "0." P1DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. A reset initializes P1DDR to H'03, so that pins P11 and P10 carry clock outputs and the other pins are set for input. In the hardware standby mode, P1DDR is cleared to H'00, stopping the clock outputs. P1DDR is not initialized in the software standby mode, so if a P1DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 1 data register (or the o or E clock). 2. Port 1 Data Register (P1DR)--H'FF82
Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 -- R 0 P10 -- R
P1DR is an 8-bit register containing the data for pins P17 to P10. When the CPU reads P1DR, for output pins it reads the value in the P1DR latch, but for input pins, it obtains the pin status directly. Note that when pins P11 and P10 are used for output, they output the clock signals (o and E), not the contents of P1DR. If the CPU reads Pl1 and Pl0 (when Pl1DDR = Pl0DDR = 1), it obtains the clock values at the current instant. 3. Port 1 Control Register (P1CR)--H'FFFC
Bit 7 -- Initial value Read/Write 1 -- 6 IRQ1E 0 R/W 5 IRQ0E 0 R/W 4 NMIEG 0 R/W 3 BRLE 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
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P1CR selects the functions of four of the port 1 pins. It also selects the input edge of the NMI pin. At a reset and in the hardware standby mode, P1CR is initialized to H'87. It is not initialized in the software standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as "1." Bit 6--Interrupt Request 1 Enable (IRQ1E): This bit selects the function of pin P16.
Bit 6 IRQ1E 0 1
Description P16 functions as an input/output pin. (Initial value) P16 functions as the IRQ1 input pin, regardless of the value set in P16DDR. (However, the CPU can still read the pin status by reading P1DR.)
Bit 5--Interrupt Request 0 Enable (IRQ0E): This bit selects the function of pin P15.
Bit 5 IRQ0E 0 1
Description (Initial value) P15 functions as an input/output pin. P15 functions as the IRQ0 input pin, regardless of the value set in P15DDR. (However, the CPU can still read the pin status by reading P1DR.)
Bit 4--Nonmaskable Interrupt Edge (NMIEG): This bit selects the input edge of the NMI pin. It is not related to port 0.
Bit 4 NMIEG 0 1
Description A nonmaskable interrupt is generated on the falling edge of the input at the NMI pin. A nonmaskable interrupt is generated on the rising edge of the input at the NMI pin.
(Initial value)
Bit 3--Bus Release Enable (BRLE): This bit selects the functions of pins P12 and P13. It is valid only in the expanded modes (modes 1, 2, 3, and 4). In the single-chip mode, pins P12 and P13 function as input/output pins regardless of the value of the BRLE bit.
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Bit 3 BRLE 0 1
Description P13 and P12 function as input/output pins. P13 functions as the input pin. P12 functions as the output pin.
(Initial value)
Bits 2 to 0--Reserved: These bits cannot be modified and are always read as "1." 9.2.3 Pin Functions in Each Mode Port 1 operates differently in the expanded modes (modes 1, 2, 3, and 4) and the single-chip mode (mode 7). Table 9-3 explains how the pin functions are selected in the expanded mode. Table 9-4 explains how the pin functions are selected in the single-chip mode. Table 9-3 Port 1 Pin Functions in Expanded Modes
Pin Functions and How they are Selected P17 / TMO The function depends on output select bits 3 to 0 (OS3 to OS0) of the 8-bit timer control/status register (TCSR) and on the P17DDR bit as follows: OS3 to OS0 P17DDR Pin function All four bits are "0" 0 1 P17 output P17 input At least one bit is "1" 0 1 TMO output
P16 / IRQ1 The function depends on the IRQ1E bit and the P16DDR bit as follows: IRQ1E P16DDR Pin function 0 0 P16 input 1 P16 output 0 IRQ1 input 1 1
P15 / IRQ0 The function depends on the IRQ0E bit and the P15DDR bit as follows: IRQ0E P15DDR Pin function 0 0 P15 input 1 P15 output 0 IRQ0 input 1 1
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Table 9-3 Port 1 Pin Functions in Expanded Modes (cont)
Pin P14 / WAIT Functions and How they are Selected The function depends on the wait mode select 1 bit (WMS1) of the wait-state control register (WCR) and the P14DDR bit as follows: WMS1 P14DDR Pin function P13 / BREQ 0 0 P14 input 1 P14 output 0 WAIT input 1 1
The function depends on the BRLE bit and the P13DDR bit as follows: BRLE P13DDR Pin function 0 0 P13 input 1 P13 output 1 0 1 BREQ input
P12 / BACK
The function depends on the BRLE bit and the P12DDR bit as follows: BRLE P12DDR Pin function 0 0 P12 input 1 P12 output 0 BACK input 1 1
P11 / E P11DDR Pin function P10 / o P10DDR Pin function 0 Input 1 o clock output 0 Input 1 E clock output
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Table 9-4 Port 1 Pin Functions in Single-Chip Modes
Pin P17 / TMO Selection of Pin Functions The function depends on output select bits 3 to 0 (OS3 to OS0) of the 8-bit timer control/status register (TCSR) and on the P17DDR bit as follows: OS3 to OS0 P17DDR Pin function P16 / IRQ1 All four bits are "0" 0 1 P17 output P17 input At least one bit is "1" 0 1 TMO output
The function depends on the IRQ1E bit and the P16DDR bit as follows: IRQ1E P16DDR Pin function 0 0 P16 input 1 P16 output 0 IRQ1 input 1 1
P15 / IRQ0
The function depends on the IRQ0E bit and the P15DDR bit as follows: IRQ0E P15DDR Pin function 0 0 P15 input 1 P15 output 0 IRQ0 input 1 1
P14 P14DDR Pin function P13 P13DDR Pin function 0 Input 1 Output 0 Input 1 Output
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Table 9-4 Port 1 Pin Functions in Single-Chip Modes (cont)
Pin P12 Selection of Pin Functions P12DDR Pin function P11 / E P11DDR Pin function P10 / o P10DDR Pin function 0 Input 1 o clock output 0 Input 1 E clock output 0 Input 1 Output
9.3 Port 2
9.3.1 Overview Port 2 is a five-bit input/output port with the pin configuration shown in figure 9-2. It functions as an input/output port only in the single-chip mode. In the expanded modes it is used for output of bus control signals. Outputs from port 2 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair.
Pin P24 / WR P23 / RD P22 / DS P21 / R/W P20 / AS Expanded Modes WR (output) RD (output) DS (output) R/W (output) AS (output) Single-Chip Mode P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output)
Port 2
Figure 9-2 Pin Functions of Port 2
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9.3.2 Port 2 Registers Register Configuration: Table 9-5 lists the registers of port 2. Table 9-5 Port 2 Registers
Name Port 2 data direction register Port 2 data register Abbreviation P2DDR P2DR Read/Write W R/W Initial Value H'E0 H'E0 Address H'FF81 H'FF83
1. Port 2 Data Direction Register (P2DDR)--H'FF81
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 3 2 1 0
P24DDR P23DDR P22DDR P21DDR P20DDR 0 W 0 W 0 W 0 W 0 W
P2DDR is an 8-bit register that selects the direction of each pin in port 2. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P2DDR is set to "1," and as an input pin if the bit is cleared to "0." Bits 4 to 0 can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. Bits 7 to 5 are reserved. They cannot be modified and are always read as "1." At a reset and in the hardware standby mode, P2DDR is initialized to H'E0, making all five pins input pins. P2DDR is not initialized in the software standby mode, so if a P2DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 2 data register. Expanded Modes: All bits of P2DDR are fixed at "1" and cannot be modified.
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2. Port 2 Data Register (P2DR)--H'FF83
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W
P2DR is an 8-bit register containing the data for pins P24 to P20. Bits 7 to 5 are reserved. They cannot be modified and are always read as "1." When the CPU reads P2DR, for output pins it reads the value in the P2DR latch, but for input pins, it obtains the pin status directly. 9.3.3 Pin Functions in Each Mode Port 2 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). Separate descriptions are given below. Pin Functions in Expanded Modes: In the expanded modes (modes 1, 2, 3, and 4), all pins of P2DDR is automatically set to "1" for output. Port 2 outputs the bus control signals (AS, R/W, DS, RD, WR). Figure 9-3 shows the pin functions in the expanded modes.
Port 2
WR RD DS R/W AS
(output) (output) (output) (output) (output)
Figure 9-3 Port 2 Pin Functions in Expanded Modes
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Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 2 pins can be designated as an input pin or an output pin, as indicated in figure 9-4, by setting the corresponding bit in P2DDR to "1" for output or clearing it to "0" for input.
Port 2
P24 P23 P22 P21 P20
(input/output) (input/output) (input/output) (input/output) (input/output)
Figure 9-4 Port 2 Pin Functions in Single-Chip Mode
9.4 Port 3
9.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9-5. In the expanded modes it operates as the external data bus (D7 - D0). In the single-chip mode it operates as a general-purpose input/output port. Outputs from port 3 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair.
Pin P37 / D7 P36 / D6 P35 / D5 P34 / D4 P33 / D3 P32 / D2 P31 / D1 P30 / D0 Expanded Modes D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Single-Chip Mode P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output)
Port 3
Figure 9-5 Pin Functions of Port 3
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9.4.2 Port 3 Registers Register Configuration: Table 9-6 lists the registers of port 3. Table 9-6 Port 3 Registers
Name Port 3 data direction register Port 3 data register Abbreviation P3DDR P3DR Read/Write W R/W Initial Value H'00 H'00 Address H'FF84 H'FF86
1. Port 3 Data Direction Register (P3DDR)--H'FF84
Bit 7 6 5 4 3 2 1 0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P3DDR is an 8-bit register that selects the direction of each pin in port 3. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P3DDR is set to "1," and as an input pin if the bit is cleared to "0." P3DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. At a reset and in the hardware standby mode, P3DDR is initialized to H'00, making all eight pins input pins. P3DDR is not initialized in the software standby mode, so if a P3DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 3 data register. Expanded Modes: P3DDR is not used.
152
2. Port 3 Data Register (P3DR)--H'FF86
Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W
P3DR is an 8-bit register containing the data for pins P37 to P30. At a reset and in the hardware standby mode, P3DR is initialized to H'00. When the CPU reads P3DR, for output pins it reads the value in the P3DR latch, but for input pins, it obtains the pin status directly. 9.4.3 Pin Functions in Each Mode Port 3 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). Separate descriptions are given below. Pin Functions in Expanded Modes: In the expanded modes (modes 1, 2, 3, and 4), port 3 is automatically used as the data bus and P3DDR is ignored. Figure 9-6 shows the pin functions for the expanded modes.
D7 D6 D5 D4 D3 D2 D1 D0 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Port 3
Figure 9-6 Port 3 Pin Functions in Expanded Modes
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Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 3 pins can be designated as an input pin or an output pin, as indicated in figure 9-7, by setting the corresponding bit in P3DDR to "1" for output or clearing it to "0" for input.
P37 P36 P35 P34 P33 P32 P31 P30 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Port 3
Figure 9-7 Port 3 Pin Functions in Single-Chip Mode
9.5 Port 4
9.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9-8. In the expanded modes it provides the low bits (A7 - A0) of the address bus. In the single-chip mode it operates as a general-purpose input/output port. Outputs from port 4 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair or LED (with 8mA current sink).
Pin P47 / A7 P46 / A6 P45 / A5 P44 / A4 P43 / A3 P42 / A2 P41 / A1 P40 / A0 Expanded Modes A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Single-Chip Mode P47 (input/output) P46 (input/output) P45 (input/output) P44 (input/output) P43 (input/output) P42 (input/output) P41 (input/output) P40 (input/output)
Port 4
Figure 9-8 Pin Functions of Port 4
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9.5.2 Port 4 Registers Register Configuration: Table 9-7 lists the registers of port 4. Table 9-7 Port 4 Registers
Name Port 4 data direction register Port 4 data register Abbreviation P4DDR P4DR Read/Write W R/W Initial Value H'00 H'00 Address H'FF85 H'FF87
1. Port 4 Data Direction Register (P4DDR)--H'FF85
Bit 7 6 5 4 3 2 1 0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P4DDR is an 8-bit register that selects the direction of each pin in port 4. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P4DDR is set to "1," and as in input pin if the bit is cleared to "0." P4DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. At a reset and in the hardware standby mode, P4DDR is initialized to H'00, making all eight pins input pins. P4DDR is not initialized in the software standby mode, so if a P4DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 4 data register. Expanded Modes: All bits of P4DDR are fixed at "1" and cannot be modified.
155
2. Port 4 Data Register (P4DR)--H'FF87
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W
P4DR is an 8-bit register containing the data for pins P47 to P40. At a reset and in the hardware standby mode, P4DR is initialized to H'00. When the CPU reads P4DR, for output pins it reads the value in the P4DR latch, but for input pins, it obtains the pin status directly. 9.5.3 Pin Functions in Each Mode Port 4 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). Separate descriptions are given below. Pin Functions in Expanded Modes: In the expanded modes (modes 1, 2, 3, and 4), port 4 is used for output of the low bits (A7 - A0) of the address bus. P4DDR is automatically set for output. Figure 9-9 shows the pin functions for the expanded modes.
A7 A6 A5 A4 A3 A2 A1 A0 (output) (output) (output) (output) (output) (output) (output) (output)
Port 4
Figure 9-9 Port 4 Pin Functions in Expanded Modes Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 4 pins can be designated as an input pin or an output pin, as indicated in figure 9-10, by setting the corresponding bit in P4DDR to "1" for output or clearing it to "0" for input.
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Port 4
P47 P46 P45 P44 P43 P42 P41 P40
(input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Figure 9-10 Port 4 Pin Functions in Single-Chip Mode
9.6 Port 5
9.6.1 Overview Port 5 is an 8-bit input/output port with the pin configuration shown in figure 9-11. In the expanded modes that use the on-chip ROM (modes 2 and 4), the pins of port 5 function either as general-purpose input pins or as bits A15 - A8 of the address bus, depending on the port 5 data direction register (P5DDR). Port 5 has built-in MOS pull-ups that can be turned on or off under program control. Outputs from port 5 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair.
Pin P57 / A15 P56 / A14 P55 / A13 P54 / A12 P53 / A11 P52 / A10 P51 / A9 P50 / A8 Modes 1 and 3 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Modes 2 and 4 P57 (input) / A15 (output) P56 (input) / A14 (output) P55 (input) / A13 (output) P54 (input) / A12 (output) P53 (input) / A11 (output) P52 (input) / A10 (output) P51 (input) / A9 (output) P50 (input) / A8 (output) Single-Chip Mode P57 (input/output) P56 (input/output) P55 (input/output) P54 (input/output) P53 (input/output) P52 (input/output) P51 (input/output) P50 (input/output)
Port 5
Figure 9-11 Pin Functions of Port 5
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9.6.2 Port 5 Registers Register Configuration: Table 9-8 lists the registers of port 5. Table 9-8 Port 5 Registers
Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR Read/Write W R/W Initial Value H'00 H'00 Address H'FF88 H'FF8A
1. Port 5 Data Direction Register (P5DDR)--H'FF88
Bit 7 6 5 4 3 2 1 0
P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P5DDR is an 8-bit register that selects the direction of each pin in port 5. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P5DDR is set to "1," and as an input pin if the bit is cleared to "0." P5DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. At a reset and in the hardware standby mode, P5DDR is initialized to H'00, making all eight pins input pins. P5DDR is not initialized in the software standby mode, so if a P5DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 5 data register. Expanded Modes Using On-Chip ROM (Modes 2 and 4): If a "1" is set in P5DDR, the corresponding pin is used for address output. If a "0" is set in P5DDR, the pin is used for general-purpose input. P5DDR is initialized to H'00 at a reset and in the hardware standby mode. Expanded Modes Not Using On-Chip ROM (Modes 1 and 3): All bits of P5DDR are fixed at "1" and cannot be modified.
158
Port 5 Data Register (P5DR)--H'FF8A
Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W
P5DR is an 8-bit register containing the data for pins P57 to P50. At a reset and in the hardware standby mode, P5DR is initialized to H'00. When the CPU reads P5DR, for output pins it reads the value in the P5DR latch, but for input pins, it obtains the pin status directly. 9.6.3 Pin Functions in Each Mode Port 5 operates in one way in modes 1 and 3, in another way in modes 2 and 4, and in a third way in mode 7. Separate descriptions are given below. Pin Functions in Modes 1 and 3: In modes 1 and 3 (expanded modes in which the on-chip ROM is not used), all bits of P5DDR are automatically set to "1" for output, and the pins of port 5 carry bits A15 - A8 of the address bus. Figure 9-12 shows the pin functions for modes 1 and 3.
A15 A14 A13 A12 A11 A10 A9 A8 (output) (output) (output) (output) (output) (output) (output) (output)
Port 5
Figure 9-12 Port 5 Pin Functions in Modes 1 and 3
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Pin Functions in Modes 2 and 4: In modes 2 and 4, (expanded modes in which the on-chip ROM is used), software can select whether to use port 5 for general-purpose input, or for output of bits A15 - A8 of the address bus. If a bit in P5DDR is set to "1," the corresponding pin is used for address output. If the bit is cleared to "0," the pin is used for input. A reset clears all P5DDR bits to "0," so before the address bus is used, all necessary bits in P5DDR must be set to "1." Figure 9-13 shows the pin functions in modes 2 and 4.
When P5DDR Bit is Set to "1" A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When P5DDR Bit is Cleared to "0" P57 (input) P56 (input) P55 (input) P54 (input) P53 (input) P52 (input) P51 (input) P50 (input)
Port 5
Figure 9-13 Port 5 Pin Functions in Modes 2 and 4 Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 5 pins can be designated as an input pin or an output pin, as indicated in figure 9-14, by setting the corresponding bit in P5DDR to "1" for output or clearing it to "0" for input.
P57 P56 P55 P54 P53 P52 P51 P50 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Port 5
Figure 9-14 Port 5 Pin Functions in Single-Chip Mode
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9.6.4 Built-In MOS Pull-Up The MOS input pull-ups of port 5 are turned on by clearing the corresponding bit in P5DDR to "0" and writing a "1" in P5DR. These pull-ups are turned off at a reset and in the hardware standby mode. Table 9-9 indicates the status of the MOS pull-ups in various modes. Table 9-9 Status of MOS Pull-Ups for Port 5
Mode Reset Hardware Standby Mode 1 OFF OFF 2 3 4 7 * Including the software standby mode. Other Operating States* OFF ON/OFF OFF ON/OFF
Notation: OFF: ON/OFF:
The MOS pull-up is always off. The MOS pull-up is on when P5DDR = 0 and P5DR = 1, and off otherwise.
Note on Usage of MOS Pull-Ups If the bit manipulation instructions listed below are executed on input/output ports 5 and 6 which have selectable MOS pull-ups, the logic levels at input pins will be transferred to the DR latches, causing the MOS pull-ups to be unintentionally switched on or off. This can occur with the following bit manipulation instructions: BSET, BCLR, BNOT (1) Specific Example (BSET Instruction): An example will be shown in which the BSET instruction is executed for port 5 under the following conditions: P57: Input pin, low, MOS pull-up transistor on P56: Input pin, high, MOS pull-up transistor off P55 - P50: Output pins, low The intended purpose of this BSET instruction is to switch the output level at P50 from low to high.
161
A: Before Execution of BSET Instruction
P57 Input Low 0 1 On P56 Input High 0 0 Off P55 Output Low 1 0 Off P54 Output Low 1 0 Off P53 Output Low 1 0 Off P52 Output Low 1 0 Off P51 Output Low 1 0 Off P50 Output Low 1 0 Off
Input/output Pin state DDR DR Pull-up
B: Execution of BSET Instruction BSET.B #0 @PORT5 ;set bit 0 in data register
C: After Execution of BSET Instruction
P57 Input Low 0 0 Off P56 Input High 0 1 On P55 Output Low 1 0 Off P54 Output Low 1 0 Off P53 Output Low 1 0 Off P52 Output Low 1 0 Off P51 Output Low 1 0 Off P50 Output High 1 1 Off
Input/output Pin state DDR DR Pull-up
Explanation: To execute the BSET instruction, the CPU begins by reading port 5. Since P57 and P56 are input pins, the CPU reads the level of these pins directly, not the value in the data register. It reads P57 as low (0) and P56 as high (1). Since P55 to P50 are output pins, for these pins the CPU reads the value in the data register (0). The CPU therefore reads the value of port 5 as H'40, although the actual value in P5DR is H'80. Next the CPU sets bit 0 of the read data to 1, changing the value to H'41. Finally, the CPU writes this value (H'41) back to P5DR to complete the BSET instruction. As a result, bit P50 is set to 1, switching pin P50 to high output. In addition, bits P57 and P56 are both modified, changing the on/off settings of the MOS pull-up transistors of pins P57 and P56. Programming Solution: The switching of the pull-ups for P57 and P56 in the preceding example can be avoided by using a byte in RAM as a work area for P5DR, performing bit manipulations on the work area, then writing the result to P5DR.
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A: Before Execution of BSET Instruction MOV.B MOV.B MOV.B #80, R0 R0, @RAM0 R0, @PORT5
P57 Input Low 0 1 On 1 P56 Input High 0 0 Off 0
;write data (H'80) for data register ;write to work area (RAM0) ;write to P5DR
P55 Output Low 1 0 Off 0 P54 Output Low 1 0 Off 0 P53 Output Low 1 0 Off 0 P52 Output Low 1 0 Off 0 P51 Output Low 1 0 Off 0 P50 Output Low 1 0 Off 0
Input/output Pin state DDR DR Pull-up RAM0
B: Execution of BSET Instruction BSET.B #0, @RAM0 ;set bit 0 in work area (RAM0)
C: After Execution of BSET Instruction MOV.B @RAM0, R0 MOV.B R0, @PORT5
P57 Input Low 0 1 On 1 P56 Input High 0 0 Off 0
;get value in work area (RAM0) ;write value to P5DR
P55 Output Low 1 0 Off 0 P54 Output Low 1 0 Off 0 P53 Output Low 1 0 Off 0 P52 Output Low 1 0 Off 0 P51 Output Low 1 0 Off 0 P50 Output High 1 1 Off 0
Input/output Pin state DDR DR Pull-up RAM0
9.7 Port 6
9.7.1 Overview Port 6 is a 4-bit input/output port with the pin configuration shown in figure 9-15. In mode 4 (the expanded maximum mode that uses the on-chip ROM), the pins of port 6 function either as general-purpose input pins or as the page address bus, depending on the port 6 data direction register (P6DDR). Port 6 has built-in MOS pull-ups that can be turned on or off under program control. Outputs from port 6 can drive one TTL load and a 90pF capacitive load. They can also drive a Darlington transistor pair.
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Pin P63 / A19 P62 / A18 P61 / A17 P60 / A16
Mode 3 A19 A18 A17 A16 (output) (output) (output) (output)
Mode 4 P63 P62 P61 P60 (input) / A19 (input) / A18 (input) / A17 (input) / A16 (output) (output) (output) (output)
Port 6
Mode 1 and 2 and Single-Chip Mode P63 (input/output) P62 (input/output) P61 (input/output) P60 (input/output)
Figure 9-15 Pin Functions of Port 6 9.7.2 Port 6 Registers Register Configuration: Table 9-10 lists the registers of port 6. Table 9-10 Port 6 Registers
Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR Read/Write W R/W Initial Value H'F0 H'F0 Address H'FF89 H'FF8B
1. Port 6 Data Direction Register (P6DDR)--H'FF89
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 2 1 0
P63DDR P62DDR P61DDR P60DDR 0 W 0 W 0 W 0 W
P6DDR is an 8-bit register that selects the direction of each pin in port 6. Single-Chip Mode and Expanded Minimum Modes: A pin functions as an output pin if the corresponding bit in P6DDR is set to "1," and as an input pin if the bit is cleared to "0." Bits 3 to 0 can be written but not read. An attempt to read these bits does not cause an error, but all bits are read as "1," regardless of their true values.
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Bits 7 to 4 are reserved. They cannot be modified and are always read as "1." At a reset and in the hardware standby mode, P6DDR is initialized to H'F0, making all four pins input pins. P6DDR is not initialized in the software standby mode, so in the single-chip mode, or expanded minimum mode, if a P6DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 6 data register. Expanded Maximum Mode Using On-Chip ROM (Mode 4): If a "1" is set in P6DDR, the corresponding pin is used for address output. If a "0" is set in P6DDR, the pin is used for input. P6DDR is initialized to H'F0 at a reset and in the hardware standby mode. Expanded Maximum Mode Not Using On-Chip ROM (Mode 3): All bits of P6DDR are fixed at "1" and cannot be modified. 2. Port 6 Data Register (P6DR)--H'FF8B
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W
P6DR is an 8-bit register containing the data for pins P63 to P60. Bits 7 to 4 are reserved. They cannot be modified and are always read as "1." At a reset and in the hardware standby mode, P6DR is initialized to H'F0. When the CPU reads P6DR, for output pins it reads the value in the P6DR latch, but for input pins, it obtains the pin status directly. 9.7.3 Pin Functions in Each Mode The usage of port 6 depends on the MCU operating mode. Separate descriptions are given below. Pin Functions in Mode 3: In mode 3 (the expanded maximum mode in which the on-chip ROM is not used), P6DDR is automatically set for output, and the pins of port 6 carry the page address bits (A19 - A16) of the address bus. Figure 9-16 shows the pin functions for mode 3.
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Port 6
A19 A18 A17 A16
(output) (output) (output) (output)
Figure 9-16 Port 6 Pin Functions in Mode 3 Pin Functions in Mode 4: In mode 4, (the expanded maximum mode in which the on-chip ROM is used), software can select whether to use port 6 for general-purpose input, or for output of the page address bits. If a bit in P6DDR is set to "1," the corresponding pin is used for page address output. If the bit is cleared to "0," the pin is used for input. A reset initializes these pins to the general-purpose input function, so when the address bus is used, all necessary bits in P6DDR must first be set to "1." Figure 9-17 shows the pin functions in mode 4.
When P6DDR Bit Is Set to "1" A19 (output) A18 (output) A17 (output) A16 (output) When P6DDR Bit is Cleared to "0" P63 (input) P62 (input) P61 (input) P60 (input)
Port 6
Figure 9-17 Port 6 Pin Functions in Mode 4 Pin Functions in Single-Chip Mode and Expanded Minimum Modes: In the single-chip mode (mode 7) and expanded minimum modes (modes 1 and 2), each of the port 6 pins can be designated as an input pin or an output pin, as indicated in figure 9-18, by setting the corresponding bit in P6DDR to "1" for output or clearing it to "0" for input.
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Port 6
P63 P62 P61 P60
(input/output) (input/output) (input/output) (input/output)
Figure 9-18 Port 6 Pin Functions in Modes 7, 2, and 1 9.7.4 Built-in MOS Pull-Up Port 6 has programmable MOS input pull-ups which are turned on by clearing the corresponding bit in P6DDR to "0" and writing a "1" in P6DR. These pull-ups are turned off at a reset and in the hardware standby mode. Table 9-11 indicates the status of the MOS pull-ups in various modes. Table 9-11 Status of MOS Pull-Ups for Port 5
Mode Reset Hardware Standby Mode 1 OFF OFF 2 3 4 7 * Including the software standby mode. Other Operating States* ON/OFF OFF ON/OFF
Notation: OFF: ON/OFF:
The MOS pull-up is always off. The MOS pull-up is on when P6DDR = 0 and P6DR = 1, and off otherwise.
Note: When using the built-in pull-ups, see the "Note on Usage of MOS Pull-Ups" in section 9.6.4.
9.8 Port 7
9.8.1 Overview Port 7 is an 8-bit input/output port with the pin configuration shown in figure 9-19. Its pins also carry input and output signals for the on-chip free-running timers (FRT1, FRT2, and FRT3), and two input signals for the on-chip 8-bit timer.
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Port 7 has Schmitt inputs. Outputs from port 7 can drive one TTL load and a 30pF capacitive load. They can also drive a Darlington transistor pair.
P77 P76 P75 P74 P73 P72 P71 P70 (input/output) / FTOA1 (output) (input/output) / FTOB3 (output) / FTCI3 (input) (input/output) / FTOB2 (output) / FTCI2 (input) (input/output) / FTOB1 (output) / FTCI1 (input) (input/output) / FTI3 (input) /TMRI (input) (input/output) / FTI2 (input) (input/output) / FTI1 (input) (input/output) / TMCI (input)
Port 7
Figure 9-19 Pin Functions of Port 7 9.8.2 Port 7 Registers Register Configuration: Table 9-12 lists the registers of port 7. Table 9-12 Port 7 Registers
Name Port 7 data direction register Port 7 data register Abbreviation P7DDR P7DR Read/Write W R/W Initial Value H'00 H'00 Address H'FF8C H'FF8E
1. Port 7 Data Direction Register (P7DDR)--H'FF8C
Bit 7 6 5 4 3 2 1 0
P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P7DDR is an 8-bit register that selects the direction of each pin in port 7. A pin functions as an output pin if the corresponding bit in P7DDR is set to "1," and as an input pin if the bit is cleared to "0." P7DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. At a reset and in the hardware standby mode, P7DDR is initialized to H'00, setting all pins for input. P7DDR is not initialized in the software standby mode, so if a P7DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 7 data register.
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A transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 7 that were being used by an on-chip timer when the transition occurs revert to generalpurpose input or output, controlled by P7DDR and P7DR. 2. Port 7 Data Register (P7DR)--H'FF8E
Bit 7 P77 Initial value Read/Write 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W
P7DR is an 8-bit register containing the data for pins P77 to P70. When the CPU reads P7DR, for output pins it reads the value in the P7DR latch, but for input pins, it obtains the pin status directly. 9.8.3 Pin Functions The pin functions of port 7 are the same in all MCU operating modes. As figure 9-19 indicated, these pins are used for input and output of on-chip timer signals as well as for general-purpose input and output. For some pins, two or more functions can be enabled simultaneously. P77 can be used either for general-purpose input/output, or as the output pin for the output compare A signal (FTOA) from free-running timer 1. P76 to P74 can be used either for general-purpose input/output, or as the output pins for the output compare B signals (FTOB) from free-running timers 3 to 1. When used for general-purpose input and output, they can also provide external clock input (FTCI) to the free-running counters. This additional function is selected when the clock select 1 and 0 bits (CKS1 and CKS0) in the freerunning timer control registers are both set to "1." P73 to P71 function simultaneously as general-purpose input/output pins and as input pins for the input capture signals (FTI) of free-running timers 3 to 1.
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P73 and P70 can be used for timer reset input (TMRI) and timer clock input (TMCI) for the 8-bit timer, as well as for general-purpose input and output. Table 9-13 shows how the functions of the pins of port 7 are selected. Table 9-13 Port 7 Pin Functions
Pin P77 / FTOA1 Selection of Pin Functions The function depends on the output enable A bit (OEA) of the FRT1 timer control register (TCR) and on the P77DDR bit as follows: OEA P77DDR Pin function P76 / FTOB3 / FTCI3 0 0 P77 input 1 P77 output 1 0 1 FTOA1 output
The function depends on the output compare B bit (OEB) of the FRT3 timer control register (TCR) and on the P76DDR bit as follows: OEB P76DDR Pin function 0 0 1 P76 input P76 output FTCI3 input 1 0 1 FTOB3 output
P75 / FTOB2 / FTCI2
The function depends on the output compare B bit (OEB) of the FRT2 timer control register (TCR) and on the P75DDR bit as follows: OEB P75DDR Pin function 0 0 1 P75 input P75 output FTCI2 input 1 0 1 FTOB2 output
P74 / FTOB1 / FTCI1
The function depends on the output compare B bit (OEB) of the FRT1 timer control register (TCR) and on the P74DDR bit as follows: OEB P74DDR Pin function 0 0 1 P74 input P74 output FTCI1 input 1 0 1 FTOB1 output
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Table 9-13 Port 7 Pin Functions (cont)
Pin P73 / FTI3 / TMRI Selection of Pin Functions The function depends on the counter clear bits 1 and 0 (CCLR1 and CCLR0) in the timer control register (TCR) of the 8-bit timer, and on the P73DDR bit as follows: CCLR1, CCLR0: At least one bit is "0." Both bits are set to "1" P73DDR Pin function 0 1 P73 input P73 output FTI3 input and TMRI input
P72 / FTI2 P72DDR Pin function 0 1 P72 input P72 output FTI2 input
P71 / FTI1 P71DDR Pin function 0 1 P71 output P71 input FTI1 input
P70 / TMCI
This pin always has a general-purpose input/output function, and can simultaneously be used for external clock input for the 8-bit timer, depending on clock select bits 2 to 0 (CKS2, CKS1, and CKS0) in the timer control register (TCR). See section 11, "8bit Timer" for details. P70DDR Pin function 0 1 P70 input P70 output TMCI input
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9.9 Port 8
9.9.1 Overview Port 8 is an 8-bit input port that also receives inputs for the on-chip A/D converter. The pin functions are the same in all MCU operating modes, as shown in figure 9-20.
P87 P86 P85 P84 P83 P82 P81 P80 (input) / AN7 (input) (input) / AN6 (input) (input) / AN5 (input) (input) / AN4 (input) (input) / AN3 (input) (input) / AN2 (input) (input) / AN1 (input) (input) / AN0 (input)
Port 8
Figure 9-20 Pin Functions of Port 8 9.9.2 Port 8 Registers Register Configuration: Port 8 has only the data register described in table 9-14. Since it is exclusively an input port, there is no data direction register. Table 9-14 Port 8 Registers
Name Port 8 data register Abbreviation P8DR Read/Write R Address H'FF8F
1. Port 8 Data Register (P8DR)--H'FF8F
Bit 7 P87 Initial value Read/Write 0 R 6 P86 0 R 5 P85 0 R 4 P84 0 R 3 P83 0 R 2 P82 0 R 1 P81 0 R 0 P80 0 R
When the CPU reads P8DR it always reads the current status of each pin, except that during A/D conversion the pin currently being converted reads "1" regardless of the actual input voltage at that pin.
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9.10 Port 9
9.10.1 Overview Port 9 is an 8-bit input/output port with the pin configuration shown in figure 9-21. In addition to general-purpose input and output, its pins are used for the output compare A signals from freerunning timers 2 and 3, for PWM timer output, and for input and output by the on-chip serial communication interface 9 (SCI). The pin functions are the same in all MCU operating modes. Outputs from port 9 can drive one TTL load and a 30pF capacitive load. They can also drive a Darlington transistor pair.
P97 P96 P95 P94 P93 P92 P91 P90 (input/output) / SCK (input/output) (input/output) / RXD (input) (input/output) / TXD (output) (input/output) / PW3 (output) (input/output) / PW2 (output) (input/output) / PW1 (output) (input/output) / FTOA3 (output) (input/output) / FTOA2 (output)
Port 9
Figure 9-21 Pin Functions of Port 9 9.10.2 Port 9 Registers Register Configuration: Table 9-15 lists the registers of port 9. Table 9-15 Port 9 Registers
Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR Read/Write W R/W Initial Value H'00 H'00 Address H'FFFE H'FFFF
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1. Port 9 Data Direction Register (P9DDR)--H'FFFE
Bit 7 6 5 4 3 2 1 0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an output pin if the corresponding bit in P9DDR is set to "1," and as an input pin if the bit is cleared to "0." P9DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as "1," regardless of their true values. At a reset and in the hardware standby mode, P9DDR is initialized to H'00, setting all pins for input. P9DDR is not initialized in the software standby mode, so if a P9DDR bit is set to "1" when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 9 data register. A transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 9 that were being used by an on-chip module (example: free-running timer output) when the transition occurs revert to general-purpose input or output, controlled by P9DDR and P9DR. 2. Port 9 Data Register (P9DR)--H'FFFF
Bit 7 P97 Initial value Read/Write 0 R/W 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W
P9DR is an 8-bit register containing the data for pins P97 to P90. When the CPU reads P9DR, for output pins it reads the value in the P9DR latch, but for input pins, it obtains the pin status directly. 9.10.3 Pin Functions The pin functions of port 9 are the same in all MCU operating modes. As figure 9-21 indicated, these pins are used for output of on-chip timer signals and for input and output of serial data and clock signals as well as for general-purpose input and output. Specifically, they carry output signals for free-running timers 2 and 3, output signals for the pulse-width modulation (PWM) timer, and input and output signals for the serial communication interface.
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Table 9-16 shows how the functions of the pins of port 9 are selected. Table 9-16 Port 9 Pin Functions
Pin P97 / SCK Selection of Pin Functions The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of the serial communication interface as follows: C/A 0 CKE1 0 1 0 CKE0 0 1 0 1 0 1 Pin function P97 SCI SCI external SCI internal input internal clock input clock output or clock output* output * Input or output is selected by the P97DDR bit. P96 / RXD 1 1 0 1 SCI external clock input
The function depends on the receive enable bit (RE) of the serial control register (SCR) and on the P96DDR bit as follows: RE P96DDR Pin function 0 0 P96 input 1 P96 output 0 RXD input 1 1
P95 / TXD
The function depends on the transmit enable bit (TE) of the serial control register (SCR) and on the P95DDR bit as follows: TE P95DDR Pin function 0 0 P95 input 1 P95 output 0 TXD output 1 1
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Table 9-16 Port 9 Pin Functions (cont)
Pin P94 / PW3 Selection of Pin Functions The function depends on the output enable bit (OE) of the timer control register of PWM timer channel 3 and on the P94DDR bit as follows: OE P94DDR Pin function P93 / PW2 0 0 P94 input 1 P94 output 0 PW3 output 1 1
The function depends on the output enable bit (OE) of the timer control register of PWM timer channel 2 and on the P93DDR bit as follows: OE P93DDR Pin function 0 0 P93 input 1 P93 output 0 PW2 output 1 1
P92 / PW1
The function depends on the output enable bit (OE) of the timer control register of PWM timer channel 1 and on the P92DDR bit as follows: OE P92DDR Pin function 0 0 P92 input 1 P92 output 0 PW1 output 1 1
P91 / FTOA3
The function depends on the output compare A bit (OEA) of the FRT3 timer control FTOA3 register (TCR) and on the P91DDR bit as follows: OEA P91DDR Pin function 0 0 P91 input 1 P91 output 1 0 1 FTOA3 output
P90 / FTOA2
The function depends on the output compare A bit (OEA) of the FRT3 timer control FTOA2 register (TCR) and on the P90DDR bit as follows: OEA P90DDR Pin function 0 0 P90 input 1 P90 output 1 0 1 FTOA2 output
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Section 10 16-Bit Free-Running Timers
10.1 Overview
The H8/532 has an on-chip 16-bit free-running timer (FRT) module with three independent channels (FRT1, FRT2, and FRT3). All three channels are functionally identical. Each channel has a 16-bit free-running counter that it uses as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms per channel), input pulse width measurement, and measurement of external clock periods. 10.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counters can be driven by an internal clock source (o/4, o/8, or o/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each free-running timer channel can generate two independent waveforms. * Input capture function The current count can be captured on the rising or falling edge (selectable) of an input signal. * Four types of interrupts Compare-match A and B, input capture, and overflow interrupts can be requested independently. The compare-match and input capture interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A.
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10.1.2. Block Diagram Figure 10-1 shows a block diagram of one free-running timer channel.
External clock Internal clock o/4 o/8 FTCI o/32 Clock
Clock select
OCRA
Compare-match A FTOA FTOB FTI Overflow
Comparator A Bus interface Module data bus Internal data bus
FRC Clear Compare-match B Control logic Capture ICR OCRB Comparator B
TCSR
TCR ICI OCIA OCIB FOVI Interrupt signals OCRA: OCRB: FRC: ICR: TCSR: TCR: Output Compare Register A Output Compare Register B Free Running Counter Input Capture Register Timer Control/Status Register Timer Control Register
Figure 10-1 Block Diagram of 16-Bit Free-Running Timer
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10.1.3 Input and Output Pins Table 10-1 lists the input and output pins of the free-running timer module. Table 10-1 Input and Output Pins of Free-Running Timer Module
Channel Name 1 Output compare A Output compare B or counter clock input Input capture 2 Output compare A Output compare B or counter clock input Input capture 3 Output compare A Output compare B or counter clock input Input capture Abbreviation FTOA1 FTOB1 / FTCI1 FTI1 FTOA2 FTOB2 / FTCI2 FTI2 FTOA3 FTOB3 / FTCI3 FTI3 I/O Output Output / Input Input Output Output / Input Input Output Output / Input Input Function Output controlled by comparator A of FRT1 Output controlled by comparator B of FRT1, or input of external clock source for FRT1 Trigger for capturing current count of FRT1 Output controlled by comparator A of FRT2 Output controlled by comparator B of FRT2, or input of external clock source for FRT2 Trigger for capturing current count of FRT2 Output controlled by comparator A of FRT3 Output controlled by comparator B of FRT3, or input of external clock source for FRT3 Trigger for capturing current count of FRT3
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10.1.4 Register Configuration Table 10-2 lists the registers of each free-running timer channel. Table 10-2 Register Configuration
Initial Channel Name Abbreviation R/W Value Timer control register TCR R/W H'00 Timer control/status register TCSR R/(W)* H'00 Free-running counter (High) FRC (H) R/W H'00 Free-running counter (Low) FRC (L) R/W H'00 1 Output compare register A (High) OCRA (H) R/W H'FF Output compare register A (Low) OCRA (L) R/W H'FF Output compare register B (High) OCRB (H) R/W H'FF Output compare register B (Low) OCRB (L) R/W H'FF Input capture register (High) ICR (H) R H'00 Input capture register (Low) ICR (L) R H'00 Timer control register TCR R/W H'00 Timer control/status register TCSR R/(W)* H'00 Free-running counter (High) FRC (H) R/W H'00 Free-running counter (Low) FRC (L) R/W H'00 2 Output compare register A (High) OCRA (H) R/W H'FF Output compare register A (Low) OCRA (L) R/W H'FF Output compare register B (High) OCRB (H) R/W H'FF Output compare register B (Low) OCRB (L) R/W H'FF Input capture register (High) ICR (H) R H'00 Input capture register (Low) ICR (L) R H'00 * Software can write a "0" to clear bits 7 to 4, but cannot write a "1" in these bits.
Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FFA8 H'FFA9
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Table 10-2 Register Configuration (cont)
Initial Name Abbreviation R/W Value Timer control register TCR R/W H'00 Timer control/status register TCSR R/(W)* H'00 Free-running counter (High) FRC (H) R/W H'00 Free-running counter (Low) FRC (L) R/W H'00 3 Output compare register A (High) OCRA (H) R/W H'FF Output compare register A (Low) OCRA (L) R/W H'FF Output compare register B (High) OCRB (H) R/W H'FF Output compare register B (Low) OCRB (L) R/W H'FF Input capture register (High) ICR (H) R H'00 Input capture register (Low) ICR (L) R H'00 * Software can write a "0" to clear bits 7 to 4, but cannot write a "1" in these bits.
Channel
Address H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9
10.2 Register Descriptions
10.2.1 Free-Running Counter (FRC)--H'FF92, H'FFA2, H'FFB2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). The FRC can be cleared by compare-match A. When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to "1." Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written or read. See section 10.3, "CPU Interface" for details. The FRCs are initialized to H'0000 at a reset and in the standby modes.
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10.2.2 Output Compare Registers A and B (OCRA and OCRB)--H'FF94 and H'FF96, H'FFA4 and H'FFA6, H'FFB4 and H'FFB6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer control register (TCR) is set to "1," when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in the timer control status register (TCSR) is output at the output compare pin (FTOA or FTOB). The FTOA and FTOB output are "0" before the first compare-match. Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used when they are written. See section 10.3, "CPU Interface" for details. OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes. 10.2.3 Input Capture Register (ICR)--H'FF98, H'FFA8, H'FFB8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 Read/Write R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
The ICR is a 16-bit read-only register. When the rising or falling edge of the signal at the input capture input pin is detected, the current value of the FRC is copied to the ICR. At the same time, the input capture flag (ICF) in the timer control/status register (TCSR) is set to "1." The input capture edge is selected by the input edge select bit (IEDG) in the TCSR. Because the ICR is a 16-bit register, a temporary register (TEMP) is used when the ICR is written or read. See section 10.3, "CPU Interface" for details.
182
To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system clock periods (1.5*o).
o
FTI
Minimum FTI Pulse Width
The ICR is initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the ICR even if the input capture flag (ICF) is already set.
10.2.4 Timer Control Register (TCR)
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The TCR is an 8-bit readable/writable register that selects the FRC clock source, enables the output compare signals, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes. Bit 7--Input Capture Interrupt Enable (ICIE): This bit selects whether to request an input capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register (TCSR) is set to "1."
Bit 7 ICIE 0 1
Description The input capture interrupt request (ICI) is disabled. The input capture interrupt request (ICI) is enabled.
(Initial value)
Bit 6--Output Compare Interrupt Enable B (OCIEB): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control register (TCSR) is set to "1."
183
Bit 6 OCIEB 0 1
Description Output compare interrupt request B (OCIB) is disabled. Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 5--Output Compare Interrupt Enable A (OCIEA): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control register (TCSR) is set to "1."
Bit 5 OCIEA 0 1
Description Output compare interrupt request A (OCIA) is disabled. Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 4--Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a freerunning timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer status/control register (TCSR) is set to "1."
Bit 4 OVIE 0 1
Description The free-running timer overflow interrupt request (FOVI) is disabled. The free-running timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 3--Output Enable B (OEB): This bit selects whether to enable or disable output of the logic level selected by the OLVLB bit in the timer status/control register (TCSR) at the output compare B pin when the FRC and OCRB values match.
Bit 3 OEB 0 1
Description Output compare B output is disabled. Output compare B output is enabled.
(Initial value)
Bit 2--Output Enable A (OEA): This bit selects whether to enable or disable output of the logic level selected by the OLVLA bit in the timer status/control register (TCSR) at the output compare A pin when the FRC and OCRA values match.
184
Bit 2 OEA 0 1
Description Output compare A output is disabled. Output compare A output is enabled.
(Initial value)
Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Internal clock source (o/4) (Initial value) 0 1 Internal clock source (o/8) 1 0 Internal clock source (o/32) 1 1 External clock source (counted on the rising edge)* * Output enable bit (bit 3) must be cleared to "0."
10.2.5 Timer Control/Status Register (TCSR)
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)* 3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W 0 CCLRA 0 R/W
The TCSR is an 8-bit readable and partially writable* register that selects the input capture edge and output compare levels, and specifies whether to clear the counter on compare-match A. It also contains four status flags. The TCSR is initialized to H'00 at a reset and in the standby modes. * Software can write a "0" in bits 7 to 4 to clear the flags, but cannot write a "1" in these bits. Bit 7--Input Capture Flag (ICF): This status flag is set to "1" to indicate an input capture event. It signifies that the FRC value has been copied to the ICR.
185
Bit 7 ICF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ICF bit, then writes a "0" in this bit. 2. The data transfer controller (DTC) serves an input capture interrupt. This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR.
Bit 6--Output Compare Flag B (OCFB): This status flag is set to "1" when the FRC value matches the OCRB value.
Bit 6 OCFB 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the OCFB bit, then writes a "0" in this bit. 2. The data transfer controller (DTC) serves output compare interrupt B. This bit is set to 1 when FRC = OCRB.
Bit 5--Output Compare Flag A (OCFA): This status flag is set to "1" when the FRC value matches the OCRA value.
Bit 5 OCFA 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the OCFA bit, then writes a "0" in this bit. 2. The data transfer controller (DTC) serves output compare interrupt A. This bit is set to 1 when FRC = OCRA.
Bit 4--Timer Overflow Flag (OVF): This status flag is set to "1" when the FRC overflows (changes from H'FFFF to H'0000).
Bit 4 OVF 0 1
Description This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit, then writes a "0" in this bit. This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Bit 3--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match.
186
Bit 3 OLVLB 0 1
Description A "0" logic level (Low) is output for compare-match B. A "1" logic level (High) is output for compare-match B.
(Initial value)
Bit 2--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match.
Bit 2 OLVLA 0 1
Description A "0" logic level (Low) is output for compare-match A. A "1" logic level (High) is output for compare-match A.
(Initial value)
Bit 1--Input Edge Select (IEDG): This bit selects whether to capture the count on the rising or falling edge of the input capture signal.
Bit 1 IEDG 0 1
Description The FRC value is copied to the ICR on the falling edge of the input capture signal. The FRC value is copied to the ICR on the rising edge of the input capture signal.
(Initial value)
Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match).
Bit 0 CCLRA Description 0 The FRC is not cleared. (Initial value) 1 The FRC is cleared at compare-match A.
187
10.3 CPU Interface
The FRC, OCRA, OCRB, and ICR are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these four registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows. * Register Write When the CPU writes to the upper byte, the upper byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these four registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. Coding Examples : Write the contents of R0 into OCRA in FRT1 MOV.W R0, @H'FF94 : Read ICR of FRT2 MOV.W, @H'FFA8, R0 The same considerations apply to access by the DTC. Figure 10-2 shows the data flow when the FRC is accessed. The other registers are accessed in the same way, except that when OCRA or OCRB is read, the upper and lower bytes are both transferred directly to the CPU without using the temporary register.
188
< Upper byte write >
Module data bus CPU wites data H'AA Bus interface
TEMP [H'AA]
FRCH [ ]
FRCL [ ]
< Lower byte write >
Module data bus CPU wites data H'55 Bus interface
TEMP [H'AA]
FRCH [H'AA]
FRCL [H'55]
Figure 10-2 (a) Write Access to FRC (When CPU Writes H'AA55)
189
< Upper byte read >
Module data bus CPU wites data H'AA Bus interface
TEMP [H'55]
FRCH [H'AA]
FRCL [H'55]
< Lower byte read >
Module data bus CPU wites data H'55 Bus interface
TEMP [H'55]
FRCH [ ]
FRCL [ ]
Figure 10-2 (b) Read Access to FRC (When FRC Contains H'AA55)
10.4 Operation
10.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. If external clock input is selected, the FRC increments on the rising edge of the clock signal. Figure 10-3 shows the increment timing.
190
The pulse width of the external clock signal must be at least 1.5*o clock periods. The counter will not increment correctly if the pulse width is shorter than 1.5*o clock periods.
o
FTCI
Minimum FTCI Pulse Width
o
External clock source
FRC clock pulse
FRC
N
N+1
Figure 10-3 Increment Timing for External Clock Input 10.4.2 Output Compare Timing Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to "1" by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before the FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 10-4 shows the timing of the setting of the output compare flags.
191
o
O
FRC
N
N+1
OCR
N
Internal comparematch signal
OCF
Figure 10-4 Setting of Output Compare Flags Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 10-5 shows the timing of this operation for compare-match A.
o
Internal comparematch A signal OLYLA
FTOA
Figure 10-5 Timing of Output Compare A
192
FRC Clear Timing: If the CCLRA bit is set to "1," the FRC is cleared when compare-match A occurs. Figure 10-6 shows the timing of this operation.
o
Internal comparematch A signal
FRC
N
H'0000
Figure 10-6 Clearing of FRC by Compare-Match A 10.4.3 Input Capture Timing 1. Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the input at the input capture pin (FTI), as selected by the IEDG bit in the TCSR. Figure 10-7 shows the usual input capture timing when the rising edge is selected (IEDG = "1").
o
Input at FTI pin
Internal input capture signal
Figure 10-7 Input Capture Timing (Usual Case) But if the upper byte of the ICR is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. Figure 10-8 shows the timing for this case.
193
Read cycle: CPU reads upper byte of ICR T1 T2 T3
o
Input at FTI pin
Internal input capture signal
Figure 10-8 Input Capture Timing (1-State Delay) Timing of Input Capture Flag (ICF) Setting: The input capture flag (ICF) is set to "1" by the internal input capture signal. Figure 10-9 shows the timing of this operation.
o
Internal input capture signal
ICF
FRC
N-1
N
N+1
ICR
N
Figure 10-9 Setting of Input Capture Flag
194
10.4.4 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to "1" when the FRC overflows (changes from H'FFFF to H'0000). Figure 10-10 shows the timing of this operation.
o
FRC
H'FFFF
H'0000
Internal overflow signal
OVF
Figure 10-10 Setting of Overflow Flag (OVF)
10.5 CPU Interrupts and DTC Interrupts
Each free-running timer channel can request four types of interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable and flag bits are set. Independent signals are sent to the interrupt controller for each type of interrupt. Table 10-3 lists information about these interrupts. Table 10-3 Free-Running Timer Interrupts
Interrupt ICI OCIA OCIB FOVI Description Requested when ICF is set Requested when OCFA is set Requested when OCFB is set Requested when OVF is set DTC Service Available? Yes Yes Yes No Priority High
Low
The ICI, OCIA, and OCIB interrupts can be directed to the data transfer controller (DTC) to have a data transfer performed in place of the usual interrupt-handling routine. When the DTC serves one of these interrupts, it automatically clears the ICF, OCFA, or OCFB flag to "0." See section 6, "Data Transfer Controller" for further information on the DTC.
195
10.6 Synchronization of Free-Running Timers 1 to 3
10.6.1 Synchronization after a Reset The three free-running timer channels are synchronized at a reset and remained synchronized until: * the clock source is changed; * FRC contents are rewritten; or * an FRC is cleared. After a reset, each free-running counter operates on the o/4 internal clock source. 10.6.2 Synchronization by Writing to FRCs When synchronization among free-running timers 1 to 3 is lost, it can be restored by writing to the free-running counters. Synchronization on Internal Clock Source: When an internal clock is selected, free-running timers 1 to 3 can be synchronized by writing data to their free-running counters as indicated in table 10-4. Table 10-4 Synchronization by Writing to FRCs
Clock Source Write Interval o/4 4n + 1 (states) o/8 8n + 1 (states) o/32 32n + 1 (states) m, n: Arbitrary integers Write Data m (FRC1) m+n (FRC2) m + 2n (FRC3)
After writing these data, synchronization can be checked by reading the three free-running counters at the same interval as the write interval. If the read data have the same relative differences as the write data, the three free-running timers are synchronized.
196
Example a: o/4 clock source, 12-state write interval (n = 3), on-chip memory LA: LDC.B #H'FF,BR ; Initialize base register for short-format instruction (MOV:S) LDC.W #H'0700,SR ; Raise interrupt mask level to 7 MOV.W #m,R1 ; Data for free-running timer 1 MOV.W #m+3,R2 ; Data for free-running timer 2 (m + n = m + 3) MOV.W #m+6,R3 ; Data for free-running timer 3 (m + 2n = m + 2 x 3) BSR SET4 ; Call write routine .ALIGN 2 SET4:MOV:S.W R1,@H'92:8 BRN SET4:8 MOV:S.W R2,@H'A2:8 BRN SET4:8 MOV:S.W R3,@H'B2:8 RTS ; Align write instructions (MOV:S) at even address ; Write to FRC 1 (address H'FF92) 9 states ; 2-Byte dummy instruction 3 states ; Write to FRC 2 (address H'FFA2) Total 12 states ; 2-Byte dummy instruction ; Write to FRC 3 (address H'FFB2)
Example b: o/8 clock source, 16-state write interval (n = 2), on-chip memory LB: LDC.B LDC.W MOV.W MOV.W MOV.W BSR #H'FF,BR #H'0700,SR #m,R1 #m+2,R2 #m+4,R3 SET8
.ALIGN 2 SET8:MOV:S.W R1,@H'92:8 BRN SET8:8 XCH R1,R1 MOV:S.W R2,@H'A2:8 BRN SET8:8 XCH R2,R2 MOV:S.W R3,@H'B2:8 RTS
; 9 States ; 3 States ; 4 States
Total 16 states
197
Example c: o/32 clock source, 32-state write interval (n = 1), on-chip memory LC: LDC.B #H'FF,BR LDC.W #H'0700,SR MOV.W #m,R1 MOV.W #m+1,R2 MOV.W #m+2,R3 BSR SET32 .ALIGN 2 SET32: MOV:S.W R1,@H'92:8 BSR WAIT:8 MOV:S.W R2,@H'A2:8 BSR WAIT:8 MOV:S.W R3,@H'B2:8 RTS .ALIGN 2 NOP XCH R1,R1 RTS ; Align on even address ; 2 Bytes, 9 states ; 2 Bytes, 9 states Total 32 states
WAIT:
; Align on even address ; 2 States ; 4 States ; 8 States
Note: The stack is assumed to be in on-chip RAM. Example d: o/4 clock source, 20-state write interval (n = 5), external memory LD: LDC.B #H'FF,BR LDC.W #H'0700,SR ; Set interrupt mask level to 7 CLR.B @H'F8:8 ; Disable wait states MOV.W #m,R1 MOV.W #m+5,R2 MOV.W #m+10,R3 MOV:S.W R1,@H'92:8 ; 13 States Total 20 states BRN LD:8 ; 2 Bytes, 7 states MOV:S.W R2,@H'A2:8 BRN LD:8 MOV:S.W R3,@H'B2:8
198
Example e: o/8 clock source, 24-state write interval (n = 3), external memory LE: LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8"8 MOV.W #m,R1 MOV.W #m+3,R2 MOV.W #m+6,R3 MOV:S.W R1,@H'92:8 ; 13 States BRN LE:8 ; 2 Bytes, 7 states Total 24 states NOP ; 1 Byte, 4 states MOV:S.W R2,@H'A2:8 BRN LE:8 NOP MOV:S.W R3,@H'B2:8 Example f: o/32 clock source, 32-state write interval (n = 1), external memory LF: LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+1,R2 MOV.W #m+2,R3 MOV:S.W R1,@H'92:8 ; External memory, so 13 states XCH R0,R0 ; 8 states Total 32 states BRN LF:8 ; 2 Bytes, 7 states NOP ; 4 states MOV:S.W R2,@H'A2:8 XCH R0,R0 BRN LF:8 NOP MOV:S.W R3,@H'B2:8
199
Synchronization on External Clock Source: When the external clock source is selected, the free-running timers can be synchronized by halting their external clock inputs, then writing identical values in their free-running counters.
10.7 Sample Application
In the example below, one free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in the TCSR is set to "1." 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in the TCSR.
H'FFFF OCRA OCRB FRC Clear counter
------
------
FTOA pin
FTOB pin
Figure 10-11 Square-Wave Output (Example) 10.8 Application Notes Application programmers should note that the following types of contention can occur in the freerunning timers. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the clear signal takes priority and the write is not performed.
200
------
------
H'0000
Figure 10-12 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clear signal
FRC
N
H'0000
Figure 10-12 FRC Write-Clear Contention Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and the FRC is not incremented.
201
Figure 10-13 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M
Write data
Figure 10-13 FRC Write-Increment Contention
202
Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the compare-match signal is inhibited. Figure 10-14 shows this type of contention.
Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3
o
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
N
M Write data
Compare-match A or B signal Inhibited
Figure 10-14 Contention between OCR Write and Compare-Match Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10-5. The pulse that increments the FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 10-5, the changeover generates a falling edge that triggers the FRC increment pulse. Switching between an internal and external clock source can also cause the FRC to increment.
203
Table 10-5 Effect of Changing Internal Clock Sources
No. 1 Description Low Low: CKS1 and CKS0 are rewritten while both clock sources are Low. Timing Chart
Old clock source
New clock source FRC clock pulse
FRC
N CKS rewrite
N+1
2
Low High: CKS1 and CKS0 are rewritten while old clock source is Low and new clock source is High.
Old clock source
New clock source
FRC clock pulse
FRC
N
N+1
N+2
3
High Low: CKS1 and CKS0 are rewritten while old clock source is High and new clock source is Low.
Old clock source
New clock source * FRC clock pulse
FRC
N
N+1 CKS rewrite
N+2
The switching of clock sources is regarded as a falling edge that increments the FRC.
204
Table 10-5 Effect of Changing Internal Clock Sources (cont)
No. 4 Description High High: CKS1 and CKS0 are rewritten while both clock sources are High. Timing Chart
Old clock source
New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
205
Section 11 8-Bit Timer
11.1 Overview
The H8/532 chip includes a single 8-bit timer based on an 8-bit counter (TCNT). The timer has two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer is to generate a rectangular-wave output with an arbitrary duty factor. 11.1.1 Features The features of the 8-bit timer are listed below. * Selection of four clock sources The counter can be driven by an internal clock signal (o/8, o/64, or o/1024) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counter The counter can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two time constants The single timer output (TMO) is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. * Three types of interrupts Compare-match A and B and overflow interrupts can be requested independently. The compare match interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming.
207
11.1.2 Block Diagram Figure 11-1 shows a block diagram of 8-bit timer.
External clocks Internal clocks o/8 o/64 TMCI o/1024 Clock
Clock select
TCORA
Compare-match A TMO TMRI Clear Overflow
Comparator A Bus interface Module data bus Internal data bus
TCNT
Control logic
Compare-match B
Comparator B
TCORB
TCSR
TCR CMIA CMIB OVI Interrupt signals TCORA: TCORB: TCNT: TCSR: TCR: Time Constant Register A Time Constant Register B Timer Counter Timer Control/Status Register Timer Control Register
Figure 11-1 Block Diagram of 8-Bit Timer
208
11.1.3 Input and Output Pins Table 11-1 lists the input and output pins of the 8-bit timer. Table 11-1 Input and Output Pins of 8-Bit Timer
Name Timer output Timer clock input Timer reset input Abbreviation TMO TMCI TMRI I/O Output Input Input Function Output controlled by compare-match External clock source for the counter External reset signal for the counter
11.1.4 Register Configuration Table 11-2 lists the registers of the 8-bit timer. Table 11-2 8-Bit Timer Registers
Name Abbreviation R/W Initial Value Address Timer control register TCR R/W H'00 H'FFD0 Timer control/status register TCSR R/(W)* H'10 H'FFD1 Timer constant register A TCORA R/W H'FF H'FFD2 Timer constant register B TCORB R/W H'FF H'FFD3 Timer counter TCNT R/W H'00 H'FFD4 * Software can write a "0" to clear bits 7 to 5, but cannot write a "1" in these bits.
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)--H'FFD4
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from one of four clock sources. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter.
209
The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to "1." The timer counter is initialized to H'00 at a reset and in the standby modes. 11.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FFD2 and H'FFD3
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers. When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal (TMO) is controlled by these compare-match signals as specified by output select bits 1 to 0 (OS1 to OS0) in the timer status/control register (TCSR). TCORA and TCORB are initialized to H'FF at a reset and in the standby modes. 11.2.3 Timer Control Register (TCR)--H'FFD0
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes.
210
Bit 7--Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer status/control register (TCSR) is set to "1."
Bit 7 CMIEB 0 1
Description Compare-match interrupt request B (CMIB) is disabled. Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
Bit 6--Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer status/control register (TCSR) is set to "1."
Bit 6 CMIEA 0 1
Description Compare-match interrupt request A (CMIA) is disabled. Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in the timer status/control register (TCSR) is set to "1."
Bit 5 OVIE 0 1
Description The timer overflow interrupt request (OVI) is disabled. The timer overflow interrupt request (OVI) is enabled.
(Initial value)
Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input.
Bit 4 CCLR1 0 0 1 1 Bit 3 CCLR0 0 1 0 1
Description Not cleared. (Initial value) Cleared on compare-match A. Cleared on compare-match B. Cleared on rising edge of external reset input signal.
211
Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or external clock source for the timer counter. For the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges.
Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1
Description No clock source (timer stopped). (Initial value) Internal clock source (o/8). Internal clock source (o/64). Internal clock source (o/1024). No clock source (timer stopped). External clock source, counted on the rising edge. External clock source, counted on the falling edge. External clock source, counted on both the rising and falling edges.
11.2.4 Timer Control/Status Register (TCSR)
Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
The TCSR is an 8-bit readable and partially writable* register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal (TMO). The TCSR is initialized to H'10 at a reset and in the standby modes. * Software can write a "0" in bits 7 to 5 to clear the flags, but cannot write a "1" in these bits. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to "1" when the timer count matches the time constant set in TCORB.
212
Bit 7 CMFB 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the CMFB bit, then writes a "0" in this bit. 2. Compare-match interrupt B is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORB.
Bit 6--Compare-Match Flag A (CMFA): This status flag is set to "1" when the timer count matches the time constant set in TCORA.
Bit 6 CMFA 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the CMFA bit, then writes a "0" in this bit. 2. Compare-match interrupt A is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORA.
Bit 5--Timer Overflow Flag (OVF): This status flag is set to "1" when the timer count overflows (changes from H'FF to H'00).
Bit 5 OVF 0 1
Description This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit, then writes a "0" in this bit. This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4--Reserved: This bit cannot be modified and is always read as "1." Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. When all four output select bits are cleared to "0" the TMO signal is not output. The TMO output is "0" before the first compare-match.
Bit 3 OS3 0 0 1 1 Bit 2 OS2 0 1 0 1
Description No change when compare-match B occurs. (Initial value) Output changes to "0" when compare-match B occurs. Output changes to "1" when compare-match B occurs. Output inverts (toggles) when compare-match B occurs.
213
Bit 1 OS1 0 0 1 1
Bit 0 OS0 0 1 0 1
Description No change when compare-match A occurs. (Initial value) Output changes to "0" when compare-match A occurs. Output changes to "1" when compare-match A occurs. Output inverts (toggles) when compare-match A occurs.
11.3 Operation
11.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. The external clock pulse width must be at least 1.5*o clock periods for incrementation on a single edge, and at least 2.5*o clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values.
o
TMCI Minimum TMCI Pulse Width (Single-Edge Incrementation)
o
TMCI Minimum TMCI Pulse Width (Double-Edge Incrementation)
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o
O
External clock source source TCNT clock TCNT clock pulse pulse
External clock
TCNT TCNT
N-1
N
N+1
Figure 11-2 Count Timing for External Clock Input 11.3.2 Compare Match Timing Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to "1" by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 11-3 shows the timing of the setting of the compare-match flags.
215
o
O
TCNT
N
N+1
TCOR
N
Internal compare-match signal
CMF
Figure 11-3 Setting of Compare-Match Flags Output Timing: When a compare-match event occurs, the timer output (TMO) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to "0," change to "1," or toggle. Figure 11-4 shows the timing when the output is set to toggle on compare-match A.
o
Internal compare-match A signal Timer output (TMO)
Figure 11-4 Timing of Timer Output
216
Timing of Compare-Match Clear Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 11-5 shows the timing of this operation.
o
Internal compare-match signal
TCNT
N
H'00
Figure 11-5 Timing of Compare-Match Clear 11.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to "1," the timer counter is cleared on the rising edge of an external reset input. Figure 11-6 shows the timing of this operation.
o
External reset input (TMRI)
Internal clear pulse
TCNT
N-1
N
H'00
Figure 11-6 Timing of External Reset
217
11.3.4 Setting of TCNT Overflow Flag The overflow flag (OVF) is set to "1" when the timer count overflows (changes from H'FF to H'00). Figure 11-7 shows the timing of this operation.
o
O
TCNT
H'FF
H'00
Internal overflow signal
OVF
Figure 11-7 Setting of Overflow Flag (OVF)
11.4 CPU Interrupts and DTC Interrupts
The 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable and flag bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each type of interrupt. Table 11-3 lists information about these interrupts. Table 11-3 8-Bit Timer Interrupts
Interrupt CMIA CMIB OVI Description Requested when CMFA is set Requested when CMFB is set Requested when OVF is set DTC Service Available? Yes Yes No Priority High Low
The CMIA and CMIB interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it automatically clears the CMFA or CMFB flag to "0." See section 6, "Data Transfer Controller" for further information on the DTC.
218
11.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. The control bits are set as follows: 1. In the TCR, CCLR1 is cleared to "0" and CCLR0 is set to "1" so that the timer counter is cleared when its value matches the constant in TCORA. 2. In the TCSR, bits OS3 to OS0 are set to "0110," causing the output to change to "1" on compare-match A and to "0" on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required.
TCNT H'FF TCORA TCORB H'00 Clear counter
TMO pin
Figure 11-8 Example of Pulse Output
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11.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit timer. Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 11-9 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal Address bus
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 11-9 TCNT Write-Clear Contention
220
Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 11-10 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal Address bus
TCNT address
Internal write signal
TCNT clock pulse
TCNT
N
M Write data
Figure 11-10 TCNT Write-Increment Contention
221
Contention between TCOR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the comparematch signal is inhibited. Figure 11-11 shows this type of contention.
Write cycle: CPU writes to TCORA or TCORB T1 T2 T3
o
Internal address bus
TCNT address
Internal write signal
TCNT
N
N+1
TCORA or TCORB
N
M TCOR write data
Compare-match A or B signal Inhibited
Figure 11-11 Contention between TCOR Write and Compare-Match Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 11-4.
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Table 11-4 Priority Order of Timer Output
Output Selection Toggle "1" Output "0" Output No change Priority High
Low
Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in table 11-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 11-5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. Table 11-5 Effect of Changing Internal Clock Sources
No. 1 Description Low Low*1: CKS1 and CKS0 are rewritten while both clock sources are Low. Timing Chart
Old clock source
New clock source
TCNT clock pulse
TCNT
N
N+1
CKS rewrite
Note: *1 Including a transition from Low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to Low.
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Table 11-5 Effect of Changing Internal Clock Sources (cont)
No. 2 Description Timing Chart Low High*1: Old clock CKS1 and CKS0 are source rewritten while old clock source is Low and New clock new clock source is High. source
TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
3
High Low*2: CKS1 and CKS0 are rewritten while old clock source is High and new clock source is Low.
Old clock source
New clock source *3 TCNT clock pulse
TCNT
N
N+1 CKS rewrite
N+2
Note: *1 Including a transition from the stopped state to High. *2 Including a transition from High to the stopped state. *3 The switching of clock sources is regarded as a falling edge that increments the TCNT.
224
Table 11-5 Effect of Changing Internal Clock Sources (cont)
No. 4 Description High High: CKS1 and CKS0 are rewritten while both clock sources are High. Timing Chart
Old clock source
New clock source
TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
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Section 12 PWM Timer
12.1 Overview
The H8/532 has an on-chip pulse-width modulation (PWM) timer module with three independent channels (PWM1, PWM2, and PWM3). All three channels are functionally identical. Using an 8-bit timer counter, each PWM channel generates a rectangular output pulse with a duty factor of 0 to 100%. The duty factor is specified in an 8-bit duty register (DTR). 12.1.1 Features The PWM timer module has the following features: * Selection of eight clock sources * Duty factors from 0 to 100% with 1/250 resolution * Output with positive or negative logic 12.1.2 Block Diagram Figure 12-1 shows a block diagram of one PWM timer channel.
227
DTR Comparematch
PW
TCNT Module data bus TCR
Internal clock source o/2 o/8 o/32 Clock Clock select o/128 o/256 o/1024 DTR: Duty Register TCNT: Timer Counter TCR: Timer Control Register o/2048 o/4096
Figure 12-1 Block Diagram of PWM Timer 12.1.3 Input and Output Pins Table 12-1 lists the output pins of the PWM timer module. There are no input pins. Table 12-1 Output Pins of PWM Timer Module
Name PWM1 output PWM2 output PWM3 output Abbreviation PW1 PW2 PW3 I/O Output Output Output Function Pulse output from PWM timer channel 1. Pulse output from PWM timer channel 2. Pulse output from PWM timer channel 3.
228
Bus interface
Output control
Comparator
Internal data bus
12.1.4 Register Configuration The PWM timer module has three registers for each channel as listed in table12-2. Table 12-2 PWM Timer Registers
Initial Channel Name Abbreviation R/W Value Address 1 Timer control register TCR R/W H'38 H'FFC0 Duty register DTR R/W H'FF H'FFC1 Timer counter TCNT R/(W)* H'00 H'FFC2 2 Timer control register TCR R/W H'38 H'FFC4 Duty register DTR R/W H'FF H'FFC5 Timer counter TCNT R/(W)* H'00 H'FFC6 3 Timer control register TCR R/W H'38 H'FFC8 Duty register DTR R/W H'FF H'FFC9 Timer counter TCNT R/(W)* H'00 H'FFCA * The timer counters are read/write registers, but the write function is for test purposes only. Application programs should never write to these registers.
12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)--H'FFC2, H'FFC4, H'FFCA
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The PWM timer counters (TCNT) are 8-bit up-counters. When the output enable bit (OE) in the timer control register (TCR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0). After counting from H'00 to H'F9, the timer counter repeats from H'00. The PWM timer counters can be read and written, but the write function is for test purposes only. Application software should never write to a PW timer counter, because this may have unpredictable effects.
229
The PWM timer counters are initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared to 0. 12.2.2 Duty Register (DTR)--H'FFC1, H'FFC5, H'FFC9
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The duty registers (DTR) specify the duty factor of the output pulse. Any duty factor from 0 to 100% can be selected, with a resolution of 1/250. Writing 0 (H'00) in a DTR gives a 0% duty factor; writing 125 (H'7D) gives a 50% duty factor; writing 250 (H'FA) gives a 100% duty factor. The timer count is continually compared with the DTR contents. If the DTR value is not 0, when the count increments from H'00 to H'01 the PWM output signal is set to 1. When the count increments to the DTR value, the PWM output returns to 0. If the DTR value is 0 (duty factor 0%), the PWM output remains constant at 0. The DTRs are double-buffered. A new value written in a DTR while the timer counter is running does not become valid until after the count changes from H'F9 to H'00. When the timer counter is stopped (while the OE bit is 0), new values become valid as soon as written. When a DTR is read, the value read is the currently valid value. The DTRs are initialized to H'FF at a reset and in the standby modes. 12.2.3 Timer Control Register (TCR)--H'FFC0, H'FFC4, H'FFC8
Bit 7 OE Initial value Read/Write 0 R/W 6 OS 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM outputs. The TCRs are initialized to H'38 at a reset and in the standby modes.
230
Bit 7--Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 7 OE 0 1
Description PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value) PWM output is enabled. TCNT runs.
Bit 6--Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bit 6 OS 0 1
Description Positive logic; positive-going PWM pulse, 1 = High Negative logic; negative-going PWM pulse, 1 = Low
(Initial value)
Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o).
Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1
Description o/2 (Initial value) o/8 o/32 o/128 o/256 o/1024 o/2048 o/4096
From the clock source frequency, the resolution, period, and frequency of the PWM output can be calculated as follows. Resolution = 1/clock source frequency PWM period = resolution x 250 PWM frequency = 1/PWM period If the o clock frequency is 10MHz, then the resolution, period, and frequency of the PWM output for each clock source are given in table12-3.
231
Table 12-3
PWM Timer Parameters for 10MHz System Clock
Resolution 200ns 800ns 3.2s 12.8s 25.6s 102.4s 204.8s 409.6s PWM Period 50s 200s 800s 3.2ms 6.4ms 25.6ms 51.2ms 102.4ms PWM Frequency 20kHz 5kHz 1.25kHz 312.5Hz 156.3Hz 39.1Hz 19.5Hz 9.8Hz
Internal Clock Frequency o/2 o/8 o/32 o/128 o/256 o/1024 o/2048 o/4096
12.3 Operation
Figure 12-2 shows the timing of the PWM timer operation. 1. Positive Logic (OS = "0") (1) When OE = "0"--(a) in figure 12-2: The timer count is held at H'00 and PWM output is inhibited. (The pin is used for port 9 input/output, and its state depends on the corresponding port 9 data register and data direction register.) Any value (such as N in figure 12-2) written in the DTR becomes valid immediately. (2) When OE = "1" i) The timer counter begins incrementing, and the PWM output goes High. [(b) in figure 12-2] ii) When the count reaches the DTR value, the PWM output goes Low. [(c) in figure 12-2] iii)If the DTR value is changed (by writing the data "M" in figure 12-2), the new value becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 12-2] 2. Negative Logic (OS = "1"): The operation is the same except that High and Low are reversed in the PWM output. [(e) in figure 12-2]
232
o
TCNT clock pulses
OE N-1 (a) H'00 (b) H'01 H'02 N N+1 H'F9 (d) H'00 H'01
TCNT
Figure 12-2 PWM Timing
233
H'FF N written in DTR (a) * (b) * (e)
(c) N (d) M
DTR
M written in DTR (c)
(OS = "0")
PWM output
(OS = "1")
* Used for port 9 input/output: state depends on values in data register and data direction register.
12.4 Application Notes
Two notes on the use of the PWM timer module are given below. 1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS) should be made before the output enable bit (OE) is set to 1. 2. If the DTR value is H'00, the duty factor is 0% and PWM output remains constant at 0. If the DTR value is H'FA to H'FF, the duty factor is 100% and PWM output remains constant at 1. (For positive logic, 0 is Low and 1 is High. For negative logic, 0 is High and 1 is Low.)
234
Section 13 Watchdog Timer
13.1 Overview
The H8/532 has an on-chip watchdog timer (WDT) module. This module can monitor system operation by requesting a nonmaskable interrupt if a system crash allows the timer count to overflow. When this watchdog function is not needed, the WDT module can be used as an interval timer. In the interval timer mode, an IRQ0 interrupt is requested at each counter overflow. The WDT module is also used in recovering from the software standby mode. 13.1.1 Features The basic features of the watchdog timer module are summarized as follows: * Selection of eight clock sources * Selection of two modes: watchdog timer mode and interval timer mode * Counter overflow generates an interrupt request NMI request in the watchdog timer mode; IRQ0 request in the interval timer mode.
235
13.1.2 Block Diagram Figure 13-1 is a block diagram of the watchdog timer.
NMI (Watchdog timer mode) Interrupt signals IRQ 0 (Interval timer mode) Interrupt control TCSR Internal clock source O/2 o/2 O/32 o/32 O/64 o/64 Clock Clock select O/128 o/128 O/256 o/256 O512 o/512 TCNT: Timer Counter TCSR:Timer Control/Status Register O2048 o/2048 O4096 o/4096
Overflow
TCNT
Read/ write control
Internal data bus
Figure 13-1 Block Diagram of Timer Counter 13.1.3 Register Configuration Table 13-1 lists information on the watchdog timer registers. Table 13-1 Register Configuration
Initial Addresses Name Abbreviation R/W Value Write Read Timer control/status register TCSR R/(W)* H'18 H'FFED H'FFEC Timer counter TCNT R/W H'00 H'FFED H'FFED * Software can write a 0 to clear the status flag bits, but cannot write 1.
236
13.2 Register Descriptions
13.2.1 Timer Counter TCNT--H'FFED
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The watchdog timer counter (TCNT) is a readable/writable* 8-bit up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR. When the count overflows (changes from H'FF to H'00), an overflow flag (OVF) in the TCSR is set to 1. The watchdog timer counter is initialized to H'00 at a reset and when the TME bit is cleared to 0. * TCNT is write-protected by a password. See section 13.2.3, "Notes on Register Access" for details. 13.2.2 Timer Control/Status Register (TCSR)--H'FFEC (Read), H'FFED (Write)
Bit 7 OVF Initial value Read/Write 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The watchdog timer control/status register (TCSR) is an 8-bit readable/writable*2 register that selects the timer mode and clock source and performs other functions. Bits 7 to 5 are initialized to 0 at a reset and in the standby modes. Bits 2 to 0 are initialized to 0 at a reset, but retain their values in the standby modes. *1 Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. *2 The TCSR is write-protected by a password. See section 13.2.3, "Notes on Register Access" for details.
237
Bit 7--Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed.
Bit 7 OVF 0 1
Description This bit is cleared to from 1 to 0 when the CPU reads (Initial value) the OVF bit, then writes a 0 in this bit. This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 6--Timer Mode Select (WT/IT): This bit selects whether to operate in the watchdog timer mode or interval timer mode.
Bit 6 WT/IT 0 1
Description Interval timer mode (IRQ0 request) Watchdog timer mode (NMI request)
(Initial value)
Bit 5--Timer Enable (TME): This bit enables or disables the timer.
Bit 5 TME 0 1
Description TCNT is initialized to H'00 and stopped. (Initial value) TCNT runs. An interrupt is requested when the count overflows.
Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval listed in the table below is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In the interval timer mode, IRQ0 interrupts are requested at this interval.
238
Bit 2 CKS2 0 0 0 0 1 1 1 1
Bit 1 CKS1 0 0 1 1 0 0 1 1
Bit 0 CKS0 0 1 0 1 0 1 0 1
Clock Source o/2 o/32 o/64 o/128 o/256 o/512 o/2048 o/4096
Description Overflow Interval (o = 10MHz) 51.2s (Initial value) 819.2s 1.6ms 3.3ms 6.6ms 13.1ms 52.4ms 104.9ms
13.2.3 Notes on Register Access The watchdog timer's TCNT and TCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. 1. Writing to TCNT and TCSR: These registers must be written by word access. Programs cannot write to them by byte access. The word must contain the write data and a password. The watchdog timer's TCNT and TCSR registers both have the same write address. The write data must be contained in the lower byte of the word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 13-2. The result of the access depicted in figure 13-2 is to transfer the write data from the lower byte to the TCNT or TCSR.
15 Write to TCNT H'FFEC H'5A
8
7 Write data
0
15 Write to TCSR H'FFEC H'A5
8
7 Write data
0
Figure 13-2 Writing to TCNT and TCSR
239
Coding Examples: To clear TCNT to 00: To write H'4F in TCSR:
MOV.W #H'5A00, @H'FFEC MOV.W #H'A54F, @H'FFEC
2. Reading TCNT and TCSR: The read addresses are H'FFEC for TCSR and H'FFED for TCNT, as indicated in table 13-2. These two registers are read like other registers. Byte access instructions can be used. Table 13-2 Read Addresses of TCNT and TCSR
Read Address H'FFEC H'FFED Register TCSR TCNT
13.3 Operation
13.3.1 Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in the TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the watchdog timer requests a nonmaskable interrupt (NMI) as shown in figure 13-3. NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin, so the NMI interrupt-handling routine must check the OVF bit in the TCSR to determine the source of the interrupt.
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H'FF
TCNT count
H'00
Time t
WT/IT = 1 TIME = 1
H'00 written to TCNT
OVF = 1 NMI requested
Figure 13-3 Operation in Watchdog Timer Mode 13.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In the interval timer mode, an IRQ0 request is generated each time the timer count overflows. This function can be used to generate IRQ0 requests at regular intervals. See figure 13-4. IRQ0 requests from the watchdog timer module have the same vector as IRQ0 requests from the IRQ0 pin, so the IRQ0 interrupt-handling routine must check the OVF bit in the TCSR to determine the source of the interrupt.
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H'FF
TCNT count Time t H'00
WT/IT = 0 TME = 1
IRQ0 request
IRQ0 request
IRQ0 request
IRQ0 request
IRQ0 request
Figure 13-4 Operation in Interval Timer Mode 13.3.3 Operation in Software Standby Mode The watchdog timer has a special function in the software standby mode. Specific watchdog timer settings are required when the software standby mode is used. 1. Before Transition to the Software Standby Mode: The TME bit must be cleared to 0 to stop the watchdog timer counter before a transition to the software standby mode. The chip cannot enter the software standby mode while the TME bit is set to 1. Before entering the software standby mode, software should also set the clock select bits (CKS2 to CKS0) to a value that makes the timer overflow interval equal to or greater than the settling time of the clock oscillator. 2. Recovery from the Software Standby Mode: Recovery from the software standby mode can be triggered by an NMI request. In this case the recovery proceeds as follows: When an NMI request signal is received, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by the clock select bits before the software standby mode was entered. When the count overflows (H'FF H'00), the o clock is presumed to be stable and usable, clock signals are supplied to all modules on the chip, and the NMI interrupthandling routine starts executing. This timer overflow does not set the OVF flag, and the TME bit remains cleared to 0.
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13.3.4 Setting of Overflow Flag The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an NMI or IRQ0 interrupt. The timing is shown in figure 13-5.
o
TCNT
H'FF
H'00
Internal overflow signal
OVF
Figure 13-5 Setting of OVF Bit
13.4 Application Notes
1. Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 13-6.
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Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TCNT
N
M Counter write data
Figure 13-6 TCNT Write-Increment Contention 2. Changing the Clock Select Bits (CKS2 to CKS0): Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly.
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Section 14 Serial Communication Interface
14.1 Overview
The H8/532 chip includes a single-channel serial communication interface (SCI) for transferring serial data to and from other chips. The SCI supports both synchronous and asynchronous data transfer. Communication control functions are provided by eight internal registers. 14.1.1 Features The features of the on-chip serial communication interface are: * Selection of asynchronous or synchronous mode -- Asynchronous mode The SCI can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. Eight data formats are available. -- Data length: 7 or 8 bits -- Stop bit length: 1 or 2 bits -- Parity: Even, odd, or none -- Error detection: Parity, overrun, and framing errors -- Synchronous mode The SCI can communicate with chips able to synchronize data transfers with clock pulses. -- Data length: 8 bits -- Error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. * Built-in baud rate generator Any specified bit rate can be generated. * Internal or external clock source The baud rate generator can operate on an internal clock source, or an external clock signal input at the SCK pin. * Three interrupts Transmit-end, receive-end, and receive-error interrupts are requested independently. The transmit-end and receive-end interrupts can be served by the on-chip data transfer controller (DTC), providing a convenient way to transfer data with minimal CPU programming.
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14.1.2 Block Diagram Figure 14-1 shows a block diagram of serial communication interface.
Bus interface SSR SCR SMR BRR Baud-rate generator Clock TXI RXI ERI
Module data bus
Internal data bus
RDR
TDR
Internal clock source o o/4 o/16 o/64
RXD TXD
RSR
TSR Communication control Parity generator Parity check
External clock
SCK
RDR: Receive Data Register RSR: Receive Shift Register TDR: Transmit Data Register TSR: Transmit Shift Register SSR: Serial Status Register SCR: Serial Control Register SMR: Serial Mode Register BRR: Bit Rate Register
Interrupt signals
Figure 14-1 Block Diagram of Serial Communication Interface
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14.1.3 Input and Output Pins Table 14-1 lists the input and output pins used by the SCI module. Table 14-1 SCI Input/Output Pins
Name Serial clock Receive data Transmit data Abbreviation SCK RXD TXD I/O Input/output Input Output Function Serial clock input and output. Receive data input. Transmit data output.
14.1.4 Register Configuration Table 14-2 lists the SCI registers. Table 14-2 SCI Registers
Name Abbreviation R/W Initial Value Address Receive shift register RSR -- -- -- Receive data register RDR R H'00 H'FFDD Transmit shift register TSR -- -- -- Transmit data register TDR R/W H'FF H'FFDB Serial mode register SMR R/W H'04 H'FFD8 Serial control register SCR R/W H'0C H'FFDA Serial status register SSR R/(W)* H'87 H'FFDC Bit rate register BRR R/W H'FF H'FFD9 * Software can write a "0" to clear the status flag bits, but cannot write a "1."
14.2 Register Descriptions
14.2.1 Receive Shift Register (RSR)
Bit 7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
The RSR receives incoming data bits. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly.
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14.2.2 Receive Data Register (RDR)--H'FFDD
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
The RDR stores received data. As each character is received, it is transferred from the RSR to the RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the standby modes. 14.2.3 Transmit Shift Register (TSR)
Bit 7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
The TSR holds the character currently being transmitted. When transmission of this character is completed, the next character is moved from the transmit data register (TDR) to the TSR and transmission of that character begins. If the TDR does not contain valid data, the SCI stops transmitting. The CPU cannot read or write the TSR directly. 14.2.4 Transmit Data Register (TDR)--H'FFDB
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred to the TSR. Continuous data transmission is possible by writing the next byte in the TDR while the current byte is being transmitted from the TSR. The TDR is initialized to H'FF at a reset and in the standby modes.
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14.2.5 Serial Mode Register (SMR)--H'FFD8
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 -- 1 -- 1 CKS1 0 R/W 0 CKS0 0 R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby modes. Bit 7--Communication Mode (C/A): This bit selects the asynchronous or synchronous communication mode.
Bit 7 C/A 0 1
Description Asynchronous communication. (Initial value) Communication is synchronized with the serial clock.
Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode.
Bit 6 CHR 0 1
Description 8 Bits per character. 7 Bits per character.
(Initial value)
Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode.
Bit 5 PE 0 1
Description Transmit: No parity bit is added. Receive: Parity is not checked. Transmit: A parity bit is added. Receive: Parity is not checked.
(Initial value)
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Bit 4--Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0 and in the synchronous mode.
Bit 4 O/E 0 1
Description Even parity. Odd parity.
(Initial value)
Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the synchronous mode.
Bit 3 STOP 0 1
Description 1 Stop bit. 2 Stop bits.
(Initial value)
Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source when the baud rate generator is clocked from within the H8/532 chip.
Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1
Description o clock o/4 clock o/16 clock o/64 clock
(Initial value)
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14.2.6 Serial Control Register (SCR)--H'FFDA
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 -- 1 -- 2 -- 1 -- 1 CKE1 0 R/W 0 CKE0 0 R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'0C at a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1.
Bit 7 TIE 0 1
Description The transmit-end interrupt request (TXI) is disabled. The transmit-end interrupt request (TXI) is enabled.
(Initial value)
Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1. It also enables and disables the receive-error interrupt (ERI) request.
Bit 6 RIE 0 1
Description The receive-end interrupt (RXI) and receive-error interrupt (ERI) (Initial value) requests are disabled. The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are enabled.
Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TXD pin is automatically used for output. When the transmit function is disabled, the TXD pin can be used as a general-purpose I/O port.
Bit 5 TE 0 1
Description The transmit function is disabled. The TXD pin can be used as a general-purpose I/O port. The transmit function is enabled. The TXD pin is used for output.
(Initial value)
251
Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RXD pin is automatically used for input. When the receive function is disabled, the RXD pin is available as a general-purpose I/O port.
Bit 4 RE 0 1
Description The receive function is disabled. The RXD pin can be used as a general-purpose I/O port. The receive function is enabled. The RXD pin is used for input.
(Initial value)
Bits 3 and 2--Reserved: These bits cannot be modified and are always read as 1. Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal.
Bit 1 CKE1 0 1
Description Internal clock source. External clock source. (The SCK pin is used for input.)
(Initial value)
Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in synchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when the asynchronous mode is selected. For further information on the communication format and clock source selection, see tables 14-5 and 14-6 in section 14.3, "Operation."
Bit 0 CKE0 0 1
Description The SCK pin is not used by the SCI (and is available as a general-purpose I/O port). The SCK pin is used for serial clock output.
(Initial value)
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14.2.7 Serial Status Register (SSR)--H'FFDC
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
* Software can write a 0 to clear the flags, but cannot write a 1 in these bits. The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'87 at a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7 TDRE 0
1
Description This bit is cleared from 1 to 0 when: 1. The CPU reads the TDRE bit, then writes a 0 in this bit. 2. The data transfer controller (DTC) writes data in the TDR. This bit is set to 1 at the following times: 1. The chip is reset or enters a standby mode. 2. When TDR contents are transferred to the TSR. 3. When TDRE = 0 and the TE bit is cleared to 0.
(Initial value)
Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to the RDR.
Bit 6 RDRF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the RDRF bit, then writes a 0 in this bit. 2. The data transfer controller (DTC) reads the RDR. 3. The chip is reset or enters a standby mode. This bit is set to 1 when one character is received without error and transferred from the RSR to the RDR.
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Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5 ORER 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ORER bit, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1).
Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in the synchronous mode. It has no meaning in the asynchronous mode.
Bit 4 FER 0
1
Description This bit is cleared to from 1 to 0 when: 1. The CPU reads the FER bit, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if a framing error occurs (stop bit = 0).
(Initial value)
Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used.
Bit 3 PER 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the PER bit, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the bit in the SMR).
Bits 2 to 0--Reserved: These bits cannot be modified and are always read as 1.
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14.2.8 Bit Rate Register (BRR)--H'FFD9
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the bit rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 14-3 and 14-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates. Table 14-3 Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz) 2.4576 4 Error N (%) n N 86 +0.31 1 141 255 0 1 103 127 0 0 207 63 0 0 103 31 0 0 51 15 0 0 25 7 0 0 12 3 0 ---- 1 0 ---- -- -- 0 1 0 0 ----
2 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 -- -- -- -- -- N 70 207 103 51 25 12 -- -- -- -- -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- -- -- -- n 1 0 0 0 0 0 0 0 0 -- 0
Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 --
n 1 1 0 0 0 0 0 -- -- -- --
4.194304 Error N (%) 148 -0.04 108 +0.21 217 +0.21 108 +0.21 54 -0.70 26 +1.14 13 -2.48 -- -- -- -- -- -- -- --
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Table 14-3 Examples of BRR Settings in Asynchronous Mode (2)
XTAL Frequency (MHz) 6 7.3728 Error Error N (%) n N (%) 52 +0.50 2 64 +0.70 155 +0.16 1 191 0 77 +0.16 1 95 0 155 +0.16 0 191 0 77 +0.16 0 95 0 38 +0.16 0 47 0 19 -2.34 0 23 0 -- -- 0 11 0 -- -- 0 5 0 2 0 ---- -- -- -- 0 2 0
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 1 1 0 0 0 0 0 0 0 -- 0
4.9152 Error N (%) 174 -0.26 127 0 255 0 127 0 63 0 31 0 15 0 7 0 3 0 -- -- 1 0
8 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 --
n 2 1 1 0 0 0 0 -- -- 0 --
Table 14-3 Examples of BRR Settings in Asynchronous Mode (3)
XTAL Frequency (MHz) 10 12 Error N (%) n N 88 -0.25 2 106 64 +0.16 2 77 129 +0.16 1 155 64 +0.16 1 77 129 +0.16 0 155 64 +0.16 0 77 32 -1.36 0 38 15 +1.73 0 19 7 +1.73 ---- 4 0 0 5 3 +1.73 ----
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 2 1 1 0 0 0 0 0 0 0 0
9.8304 Error N (%) 86 +0.31 255 0 127 0 255 0 127 0 63 0 31 0 15 0 7 0 4 -1.70 3 0
n 2 2 1 1 0 0 0 0 0 0 0
Error (%) -0.44 0 0 0 +0.16 +0.16 +0.16 -2.34 -- 0 --
n 2 2 1 1 0 0 0 0 0 0 0
12.288 Error N (%) 108 +0.08 79 0 159 0 79 0 159 0 79 0 39 0 19 0 9 0 5 +2.40 4 0
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Table 14-3 Examples of BRR Settings in Asynchronous Mode (4)
XTAL Frequency (MHz) 16 19.6608 Error Error N (%) n N (%) 141 +0.03 2 174 -0.26 103 +0.16 2 127 0 207 +0.16 1 255 0 103 +0.16 1 127 0 207 +0.16 0 255 0 103 +0.16 0 127 0 51 +0.16 0 63 0 25 +0.16 0 31 0 12 +0.16 0 15 0 7 0 0 9 -1.70 -- -- 0 7 0
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 2 2 1 1 0 0 0 0 0 -- 0
14.7456 Error N (%) 130 -0.07 95 0 191 0 95 0 191 0 95 0 47 0 23 0 11 0 -- -- 5 0
20 n 3 2 2 1 1 0 0 0 0 0 0 N 43 129 64 129 64 129 64 32 15 9 7 Error (%) +0.88 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 0 +1.73
n 2 2 1 1 0 0 0 0 0 0 --
B = OSC x 106/[64 x 22n x (N + 1)] B: N: OSC : n: Bit rate BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o o/4 o/16 o/64
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Table 14-4 Examples of BRR Settings in Synchronous Mode
XTAL Frequency (MHz) 8 10 n N n N -- -- -- -- 2 249 -- -- 2 124 -- -- 1 249 -- -- 1 99 1 124 0 199 0 249 0 99 0 124 0 39 0 49 0 19 0 24 0 9 -- -- 0 3 0 4 0 1 -- -- 0 0 -- --
Bit Rate 100 250 500 1K 2.5M 5K 10K 25K 50K 100K 250K 500K 1M 2.5M
2 n -- 1 1 0 0 0 0 0 0 -- 0 N -- 249 124 249 99 49 24 9 4 -- 0 n -- 2 1 1 0 0 0 0 0 0 0 0
4 N -- 124 249 124 199 99 49 19 9 4 1 0
16 n -- 3 2 2 1 1 0 0 0 0 0 0 0 N -- 124 249 124 199 99 199 79 39 19 7 3 1 n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0
20 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0
Notes: Blank: No setting is available. --: A setting is available, but the bit rate is inaccurate.
B = OSC/[8 x 22n x (N + 1)] B: N: OSC : n: Bit rate BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o o/4 o/16 o/64
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14.3 Operation
14.3.1 Overview The SCI supports serial data transfer in both asynchronous and synchronous modes. The communication format depends on settings in the SMR as indicated in table 14-5. The clock source and usage of the SCK pin depend on settings in the SMR and SCR as indicated in table 14-6. Table 14-5 Communication Formats Used by SCI
SMR CHR PE 0 0 1 1 0 1 1 -- -- Stop Bit Length 1 2 1 2 1 2 1 2 --
C/A 0
STOP 0 1 0 1 0 1 0 1 --
Mode Asynchronous
Format 8-Bit data
Parity None Yes
7-Bit data
None Yes
Synchronous
8-Bit data
--
Table 14-6 SCI Clock Source Selection
SCR Clock CKE1 CKE0 Source 0 0 Internal 1 1 0 External 1 1 0 0 Internal (Sync 1 mode) 1 0 External 1 * Cannot be used by the SCI. SMR C/A 0 (Async mode)
SCK Pin I/O port* Clock output at same frequency as baud rate Clock input at 16 times the baud rate frequency Serial clock output Serial clock input
Transmitting and receiving operations in the two modes are described next.
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14.3.2 Asynchronous Mode In asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 14-2 shows the general format of one character sent or received in the asynchronous mode. The communication channel is normally held in the mark state (High). Character transmission or reception starts with a transition to the space state (Low). The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit, if present, then the stop bit or bits (High) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Idle state Start bit D0 D1 Dn Parity bit Stop bit
1 bit
7 or 8 bits
0 or 1 bit
1 or 2 bits
One character
Figure 14-2 Data Format in Asynchronous Mode 1. Data Format: Table 14-7 lists the data formats that can be sent and received in asynchronous mode. Eight formats can be selected by bits in the SMR.
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Table 14-7 Data Formats in Asynchronous Mode
SMR Bits CHR 0 0 0 0 1 1 1 1 PE 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 1 0 1 Data Format START START START START START START START START 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data STOP STOP P P STOP STOP STOP STOP STOP STOP P P STOP STOP STOP STOP
Note: START: Start bit STOP: Stop bit P: Parity bit
2. Clock: In the asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the SCK pin. Refer to table 14-6. If an external clock is input at the SCK pin, its frequency should be 16 times the desired baud rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse rises at the center of the transmit data bits. Figure 14-3 shows the phase relationship between the output clock and transmit data.
Output clock
Transmit data
Start bit
D0
D1
D2
Figure 14-3 Phase Relationship between Clock Output and Transmit Data
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3. Data Transmission and Reception * SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0, then execute the following procedure. (1) Set the desired communication format in the SMR. (2) Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) (3) Select the clock and enable desired interrupts in the SCR. (4) Set the TE and/or RE bit in the SCR to 1. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least the transfer time for 1 bit at the selected baud rate, to make sure the SCI is initialized. If an external clock is used, the clock must not be stopped. When clearing the TDRE bit during data transmission, to assure transfer of the correct data, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. * Data Transmission: The procedure for transmitting data is as follows. (1) Set up the desired transmitting conditions in the SMR, SCR, and BRR. (2) Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output and one frame* of all 1's will be transmitted, after which the SCI is ready to transmit data. (3) Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. * A frame is the data for one character, including the start bit and stop bit(s).
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(4) The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated format as follows. i) Start bit (one 0 bit) ii) Transmit data (seven or eight bits, starting from bit 0) iii) Parity bit (odd or even parity bit, or no parity bit) iv) Stop bit (one or two consecutive 1 bits) (5) Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. When the transmit function is enabled but the TDR is empty (TDRE = 1), the output at the TXD pin is held at 1 until the TDRE bit is cleared to 0. * Data Reception: The procedure for receiving data is as follows. (1) Set up the desired receiving conditions in the SMR, SCR, and BRR. (2) Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. (3) The SCI synchronizes with the incoming data by detecting the start bit, and places the received bits in the RSR. At the end of the data, the SCI checks that the stop bit is 1. If the stop bit length is 2 bits, in ZTAT versions the SCI checks that both bits are 1, but in masked-ROM versions, only the first bit is checked. (4) When a complete frame has been received, the SCI transfers the received data to the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the RDR is cleared to 0. At the same time, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. (5) The RDRF bit is cleared to 0 when the CPU reads the SSR, then writes a 0 in the RDRF bit, or when the RDR is read by the data transfer controller (DTC). The RDR is then ready to receive the next character from the RSR. When a frame is not received correctly, a receive error occurs. There are three types of receive errors, listed in table 14-8. If a receive error occurs, the RDRF bit in the SSR is not set to 1. The corresponding error flag is set to 1 instead. If the RIE bit in the SCR is set to 1, a receive-error interrupt (ERI) is requested.
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When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun error occurs, however, the RSR contents are not transferred to the RDR. If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1. To clear a receive-error flag (ORER, FER, or PER), software must read the SSR, then write a 0 in the flag bit. Table 14-8 Receive Errors
Name Overrun error Abbreviation ORER Description Reception of the next frame ends while the RDRF bit is still set to 1. The RSR contents are not transferred to the RDR. A stop bit is 0. The RSR contents are transferred to the RDR. The parity of a frame does not match the value selected by the bit in the SMR. The RSR contents are transferred to the RDR.
Framing error Parity error
FER PER
14.3.3 Synchronous Mode The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is synchronized with a serial clock pulse. Continuous data transfer is enabled by the double buffering employed in both the transmit and receive sections of the SCI. Full duplex communication is possible because the transmit and receive sections are independent. 1. Data Format: Figure 14-4 shows the communication format used in the synchronous mode. The data length is 8 bits for both the transmit and receive directions. The least significant bit (LSB) is sent and received first. Each bit of transmit data is output from the falling edge of the serial clock pulse to the next falling edge. Received bits are latched on the rising edge of the serial clock pulse.
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Transmission direction
Serial clock
Data
Bit 0 Don't-care
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Don't-care
Figure 14-4 Data Format in Synchronous Mode 2. Clock: Either the internal serial clock created by the on-chip baud rate generator or an external clock input at the SCK pin can be selected in the synchronous mode. See table 14-6 for details. 3. Data Transmission and Reception * SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0 to disable both the transmit and receive functions, then execute the following procedure. (1) Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) (2) Select the clock in the SCR. (3) Select the synchronous mode in the SMR*. (4) Set the TE and/or RE bit to 1, and enable desired interrupts in the SCR. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the SCI is initialized. * The SCK pin is used for input or output according to the C/A bit in the serial mode register (SMR) and the CKE0 and CKE1 bits in the serial control register (SCR). (See table 14-6.) To prevent unwanted output at the SCK pin, pay attention to the order in which you set SMR and SCR.
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When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. * Data Transmission: The procedure for transmitting data is as follows. (1) Set up the desired transmitting conditions in the SMR, BRR, and SCR. (2) Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output, after which the SCI is ready to transmit data. (3) Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. (4) The first byte of transmit data is transferred from the TDR to the TSR and sent, each bit synchronized with a clock pulse. Bit 0 is sent first. Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. The TDR and TSR function as a double buffer. Continuous data transmission can be achieved by writing the next transmit data in the TDR and clearing the TDRE bit to 0 while the SCI is transmitting the current data from the TSR. If an internal clock source is selected, after transferring the transmit data from the TDR to the TSR, while transmitting the data from the TSR the SCI also outputs a serial clock signal at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1), serial clock output is suspended until the next data byte is written in the TDR and the TDRE bit is cleared to 0. During this interval the TXD pin is held at the value of the last bit transmitted. If the external clock source is selected, data transmission is synchronized with the clock signal input at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1) but external clock pulses continue to arrive, the TXD pin outputs a string of bits equal to the last bit transmitted. * Data Reception: The procedure for receiving data is as follows. (1) Set up the desired receiving conditions in the SMR, BRR, and SCR.
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(2) Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. (3) Incoming data bits are latched in the RSR on eight clock pulses. When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. (4) The SCI transfers the received data byte to the RDR so that it can be read. The RDRF bit is cleared when the program reads the RDRF bit in the SSR, then writes a 0 in the RDRF bit, or when the data transfer controller (DTC) reads the RDR. The RDR and RSR function as a double buffer. Data can be received continuously by reading each byte of data from the RDR and clearing the RDRF bit to 0 before the last bit of the next byte is received. In general, an external clock source should be used for receiving data. If an internal clock source is selected, the SCI starts receiving data as soon as the RE bit is set to 1. The serial clock is also output at the SCK pin. The SCI continues receiving until the RE bit is cleared to 0. If the last bit of the next data byte is received while the RDRF bit is still set to 1, an overrun error occurs and the ORER bit is set to 1. If the RIE bit is set to 1, a receive-error interrupt (ERI) is requested. The data received in the RSR are not transferred to the RDR when an overrun error occurs. After an overrun error, reception of the next data is enabled when the ORER bit is cleared to 0. * Simultaneous Transmit and Receive: The procedure for transmitting and receiving simultaneously is as follows: (1) Set up the desired communication conditions in the SMR, BRR, and SCR. (2) Set the TE and RE bits in the SCR to 1. The TXD and RXD pins are automatically switched to output and input, respectively, and the SCI is ready to transmit and receive data. (3) Data transmitting and receiving start when the TDRE bit in the SSR is cleared to 0. (4) Data are sent and received in synchronization with eight clock pulses.
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(5) First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. If continuous data transmission is desired, the CPU must read the TDRE bit in the SSR, write the next transmit data in the TDR, then clear the TDRE bit to 0. Alternatively, the DTC can write the next transmit data in the TDR, in which case the TDRE bit is cleared automatically. If the TDRE bit is not cleared to 0 by the time the SCI finishes sending the current byte from the TSR, the TXD pin continues to output the last bit in the TSR. (6) In the receiving section, when 8 bits of data have been received they are transferred from the RSR to the RDR and the RDRF bit in the SSR is set to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. (7) To clear the RDRF bit software read the RDRF bit in the SSR, read the data in the RDR, then write a 0 in the RDRF bit. Alternatively, the DTC can read the RDR, in which case the RDRF bit is cleared automatically. For continuous data reception, the RDRF bit must be cleared to 0 before the last bit of the next byte of data is received. If the last bit of the next byte is received while the RDRF bit is still set to 1, an overrun error occurs. The error is handled as described under "Data Reception" above. The overrun error does not affect the transmit section of the SCI, which continues to transmit normally.
14.4 CPU Interrupts and DTC Interrupts
The SCI can request three types of interrupts: transmit-end (TXI), receive-end (RXI), and receive-error (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the SCR. Independent signals are sent to the interrupt controller for each type of interrupt. The transmit-end and receive-end interrupt request signals are obtained from the TDRE and RDRF flags. The receive-error interrupt request signal is the logical OR of the three error flags: overrun error (ORER), framing error (FER), and parity error (PER). Table 14-9 lists information about these interrupts.
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Table 14-9 SCI Interrupts
DTC Service Available? No Yes Yes Low
Interrupt ERI RXI TXI
Description Receive-error interrupt, requested when ORER, FER, or PER is set. Receive-end interrupt, requested when RDRF is set. Transmit-end interrupt, requested when TDRE is set.
Priority High
The TXI and RXI interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it clears the TDRE or RDRF bit to 0 under the following conditions, which differ between the two bits. When invoked by a TXI request, if the DTC writes to the TDR, it automatically clears the TDRE bit to 0. When invoked by an RXI request, if the DTC reads from the RDR, it automatically clears the RDRF bit to 0. See section 6, "Data Transfer Controller" for further information on the DTC.
14.5 Application Notes
Application programmers should note the following features of the SCI. 1. TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR contents have been moved into the TSR, the old byte will be lost. Normally, software should check that the TDRE bit is set to 1 before writing to the TDR. 2. Multiple Receive Errors: Table 14-10 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
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Table 14-10 SSR Bit States and Data Transfer When Multiple Receive Errors Occur
SSR Bits Receive Error RDRF ORER FER PER *1 Overrun error 1 1 0 0 Framing error 0 0 1 0 Parity error 0 0 0 1 Overrun + framing errors 1*1 1 1 0 *1 Overrun + parity errors 1 1 0 1 Framing + parity errors 0 0 1 1 Overrun + framing + parity errors 1*1 1 1 1 *1 Set to 1 before the overrun error occurs. *2 Yes: The RSR contents are transferred to the RDR. No: The RSR contents are not transferred to the RDR.
RSR to RDR*2 No Yes Yes No No Yes No
3. Line Break Detection: When the RXD pin receives a continuous stream of 0's in the asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from the RSR to the RDR. Software can detect the linebreak state as a framing error accompanied by H'00 data in the RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. 4. Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RXD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 14-5. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1
Sync sampling
Data sampling
Figure 14-5 Sampling Timing (Asynchronous Mode) M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)F} x 100 [%] N: N: D: L: F: (1)
Receive margin Ratio of basic clock to bit rate (16) Duty factor of clock--ratio of High pulse width to Low width (0.5 to 1.0) Frame length (9 to 12) Absolute clock frequency deviation
When D = 0.5 and F= 0 M = (0.5 -1/2 x 16) x 100 [%] = 46.875% (2)
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Section 15 A/D Converter
15.1 Overview
The H8/532 chip includes an analog-to-digital converter module which can be programmed for input of analog signal on up to eight channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 15.1.1 Features The features of the on-chip A/D module are: Eight analog input channels Sample and hold circuit 10-Bit resolution Rapid conversion Conversion time is 13.8s per channel (at o = 10MHz) * Single and scan modes -- Single mode: A/D conversion is performed once. -- Scan mode: A/D conversion is performed in a repeated cycle on one to four channels. * Four 16-bit data registers These registers store A/D conversion results for up to four channels. * A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle. This interrupt can also be served by the on-chip data transfer controller (DTC), providing a convenient way to move results into memory. * * * *
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15.1.2 Block Diagram Figure 15-1 shows a block diagram of A/D converter.
Module data bus
AVCC 10-Bit D/A AVSS
Successive approximations register
ADDRC
ADDRD
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer + o/8 - Control circuit o/16
Sample & hold circuit
ADCSR
ADDRA
ADDRB
Bus interface
Internal data bus
ADI Interrupt signal
ADDRA: ADDRB: ADDRC: ADDRD: ADCSR:
A/D Data Register A A/D Data Register B A/D Data Register C A/D Data Register D A/D Control/Status Register
Figure 15-1 Block Diagram of A/D Converter
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15.1.3 Input Pins Table 15-1 lists the input pins used by the A/D converter module. The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN0 to AN3) and analog inputs 4 to 7 (AN4 to AN7), respectively. Table 15-1 A/D Input Pins
Name Analog supply voltage Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage for the analog circuits. Ground and reference voltage for the analog circuits. Analog input pins, group 0
Analog input pins, group 1
15.1.4 Register Configuration Table 15-2 lists the registers of the A/D converter module. Table 15-2 A/D Registers
Name Abbreviation R/W Initial Value A/D data register A (High) ADDRA (H) R H'00 A/D data register A (Low) ADDRA (L) R H'00 A/D data register B (High) ADDRB (H) R H'00 A/D data register B (Low) ADDRB (L) R H'00 A/D data register C (High) ADDRC (H) R H'00 A/D data register C (Low) ADDRC (L) R H'00 A/D data register D (High) ADDRD (H) R H'00 A/D data register D (Low) ADDRD (L) R H'00 A/D control/status register ADCSR R/(W)* H'00 * Software can write "0" to clear the status flag bits but cannot write 1. Address H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8
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15.2 Register Descriptions
15.2.1 A/D Data Registers (ADDR)--H'FFE0 to H'FFE7
Bit ADDRn H Initial value Read/Write 7 AD9 0 R 6 AD8 0 R 5 AD7 0 R 4 AD6 0 R 3 AD5 0 R 2 AD4 0 R 1 AD3 0 R (n = A to D) Bit ADDRn H Initial value Read/Write 7 AD1 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R (n = A to D) 0 -- 0 R 0 AD2 0 R
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. Each result consist of 10 bits. The first 8 bits are stored in the upper byte of the data register corresponding to the selected channel. The last two bits are stored in the lower data register byte. Each data register is assigned to two analog input channels as indicated in table 15-3. The A/D data registers are always readable by the CPU. The upper byte can be read directly. The lower byte is read via a temporary register. See section 15-3, "CPU Interface" for details. The unused bits (bits 5 to 0) of the lower data register byte are always read as 0. The A/D data registers are initialized to H'0000 at a reset and in the standby modes. Table 15-3 Assignment of Data Registers to Analog Input Channels
Analog Input Channel Group 0 Group 1 AN0 AN4 AN1 AN5 AN2 AN6 AN3 AN7
A/D Data Register ADDRA ADDRB ADDRC ADDRD
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15.2.2 A/D Control/Status Register (ADCSR)--H'FFE8
Bit 7 ADF Initial value Read/Write 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
* Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the operation of the A/D converter module. The ADCSR is initialized to H'00 at a reset and in the standby modes. Bit 7--A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7 ADF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The chip is reset or placed in a standby mode. 2. The CPU reads the ADF bit, then writes a "0" in this bit. 3. An A/D interrupt is served by the data transfer controller (DTC). This bit is set to 1 at the following times: 1. Single mode: when one A/D conversion is completed. 2. Scan mode: when inputs on all selected channels have been converted.
Bit 6--A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI) when A/D conversion is completed.
Bit 6 ADIE 0 1
Description The A/D interrupt request (ADI) is disabled. The A/D interrupt request (ADI) is enabled.
(Initial value)
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Bit 5--A/D Start (ADST): The A/D converter operates while this bit is set to 1. In the single mode, this bit is automatically cleared to 0 at the end of each A/D conversion.
Bit 5 ADST 0 1
Description A/D conversion is halted. (Initial value) 1. Single mode: One A/D conversion is performed. The ADST bit is automatically cleared to 0 at the end of the conversion. 2. Scan mode: A/D conversion starts and continues cyclically on the selected channels until the ADST bit is cleared to 0.
Bit 4--Scan Mode (SCAN): This bit selects the scan mode or single mode of operation. See section 15.4, "Operation" for descriptions of these modes. The mode should be changed only when the ADST bit is cleared to 0.
Bit 4 SCAN 0 1
Description Single mode Scan mode
(Initial value)
Bit 3--Clock Select (CKS): This bit controls the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to 0.
Bit 3 CKS 0 1
Description Conversion time = 274 states Conversion time = 138 states
(Initial value)
Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select one or more analog input channels. The channel selection should be changed only when the ADST bit is cleared to 0.
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Group Select CH2 0
1
CH1 0 0 1 1 0 0 1 1
Channel Select CH0 0 1 0 1 0 1 0 1
Selected Channels Single Mode Scan Mode AN0 AN0 AN1 AN0 and AN1 AN2 AN0 to AN2 AN3 AN0 to AN3 AN4 AN4 AN5 AN4 and AN5 AN6 AN4 to AN6 AN7 AN4 to AN7
15.3 CPU Interface
The A/D data registers (ADDRA to ADDRD) are 16-bit registers. The upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (TEMP). When the CPU or DTC reads the upper byte of an A/D data register, at the same time as the upper byte is placed on the internal data bus, the lower byte is transferred to TEMP. When the lower byte is accessed, the value in TEMP is placed on the internal data bus. A program that requires all 10 bits of an A/D result should perform word access, or should read first the upper byte, then the lower byte of the A/D data register. Either way, it is assured of obtaining consistent data. Consistent data are not assured if the program reads the lower byte first. A program that requires only 8-bit A/D accuracy should perform byte access to the upper byte of the A/D data register. The value in TEMP can be left unread. Figure 15-2 shows the data flow when the CPU (or DTC) reads an A/D data register.
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< Upper byte read >
Module data bus CPU receives data H'AA Bus interface
TEMP [H'40]
ADDRn H [H'AA]
ADDRn L [H'40] (n = A to D)
< Lower byte read >
Module data bus CPU receives data H'40 Bus interface
TEMP [H'40]
ADDRn H [H'AA]
ADDRn L [H'40] (n = A to D)
Figure 15-2 Read Access to A/D Data Register (When Register Contains H'AA40)
15.4 Operation
The A/D converter performs 10 successive approximations to obtain a result ranging from H'0000 (corresponding to AVSS) to H'FFC0 (corresponding to AVCC). Only the first 10 bits of the result are significant. The A/D converter module can be programmed to operate in single mode or scan mode as explained below.
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15.4.1 Single Mode The single mode is suitable for obtaining a single data value from a single channel. A/D conversion starts when the ADST bit is set to 1. During the conversion process the ADST bit remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0. When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) is also set to 1, an A/D conversion end interrupt (ADI) is requested, so that the converted data can be processed by an interrupt-handling routine. Alternatively, the interrupt can be served by the data transfer controller (DTC). When an A/D interrupt is served by the DTC, the DTC automatically clears the ADF bit to 0. When an A/D interrupt is served by the CPU, however, the ADF bit remains set until the CPU reads the ADCSR, then writes a 0 in the ADF bit. Before selecting the single mode, clock, and analog input channel, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process in single mode when channel 1 (AN1) is selected. Figure 15-3 shows the corresponding timing chart. 1. Software clears the ADST bit to 0, then selects the single mode (SCAN = 0) and channel 1 (CH2 to CH0 = "001"), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to 1 to start A/D conversion. (Selection of mode, clock channel and setting the ADST bit can be done at same time.) Coding Example: (when using the slow clock, CKS = 0) BCLR #5, @H'FFE8 MOV.B #H'61, @H'FFE8 2. The A/D converter samples the AN1 input and converts the voltage level to a digital value. At the end of the conversion process the A/D converter transfers the result to register ADDRB, sets the ADF bit is set to 1, clears the ADST bit to 0, and halts. 3. ADF = 1 and ADIE = 1, so an A/D interrupt is requested. 4. The user-coded A/D interrupt-handling routine is started. 5. The interrupt-handling routine reads the ADCSR value, then writes a 0 in the ADF bit to clear this bit to 0. 6. The interrupt-handling routine reads and processes the A/D conversion result. 7. The routine ends.
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Steps 2 to 7 can now be repeated by setting the ADST bit to 1 again. If the data transfer enable (DTE) bit is set to 1, the interrupt is served by the data transfer controller (DTC). Steps 4 to 7 then change as follows. 4'. 5'. 6'. 7'. The DTC is started. The DTC automatically clears the ADF bit to 0. The DTC transfers the A/D conversion result from ADDRB to a specified destination address. The DTC ends.
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Interrupt (ADI) Set*
ADIE Set* Set*
A/D conversion starts
ADST Clear* Clear*
ADF
Channel 0 (AN 0 )
Waiting
Channel 1 (AN 1 ) Waiting A/D conversion Waiting
A/D conversion
Waiting
Figure 15-3 A/D Operation in Single Mode (When Channel 1 is Selected)
Waiting
283
Waiting
Channel 2 (AN 2 )
Channel 3 (AN 3 )
ADDRA Read result A/D conversion result Read result A/D conversion result
ADDRB
ADDRC
ADDRD
*
indicates execution of a software instruction
15.4.2 Scan Mode The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to 1, A/D conversion starts from the first channel selected by the CH bits. When CH2 = 0 the first channel is AN0. When CH2 = 1 the first channel is AN4. If the scan group includes more than one channel (i.e. if bit CH1 or CH0 is set), conversion of the next channel begins as soon as conversion of the first channel ends. Conversion of the selected channels continues cyclically until the ADST bit is cleared to 0. The conversion results are placed in the data registers corresponding to the selected channels. Before selecting the scan mode, clock, and analog input channels, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process when three channels in group 0 are selected (AN0, AN1, and AN2). Figure 15-4 shows the corresponding timing chart. 1. Software clears the ADST bit to 0, then selects the scan mode (SCAN = 1), scan group 0 (CH2 = 0), and analog input channels AN0 to AN2 (CH1 and CH0 = 0) and sets the ADST bit to 1 to start A/D conversion. Coding Example: (with slow clock and ADI interrupt enabled) BCLR #5, @H'FFE8 MOV.B #H'72, @FFE8 2. The A/D converter samples the input at AN0, converts the voltage level to a digital value, and transfers the result to register ADDRA. 3. Next the A/D converter samples and converts AN1 and transfers the result to ADDRB. Then it samples and converts AN2 and transfers the result to ADDRC. 4. After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF bit to 1. If the ADIE bit is set to 1, an A/D interrupt (ADI) is requested. Then the A/D converter begins converting AN0 again. 5. Steps 2 to 4 are repeated cyclically as long as the ADST bit remains set to 1. To stop the A/D converter, software must clear the ADST bit to 0.
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Note on Scan Mode: If the ADST bit is cleared to 0 while two or more channels are being converted in scan mode, incorrect values may be set in the A/D data registers. This problem is limited to ZTAT versions. It does not occur in versions with masked ROM. Solution: Read the A/D data registers only when the ADST bit is set to 1. Example: MOV.B BSET.B ADI: #5B ,@ADCSR ; 4-channel scan mode #5 ,@ADCSR ; Start conversion (set ADST) MOV.W @ADDRA , R0 ; read ADDRA MOV.W @ADDRB , R1 ; read ADDRB MOV.W @ADDRC , R2 ; read ADDRC MOV.W @ADDRD , R3 ; read ADDRD BCLR.B #5 , @ADCSR ; clear ADST BCLR.B #7 , @ADCSR ; clear ADF
The A/D data registers should be read before ADST is cleared, as in the preceding example. (It is not necessary to clear ADST in order to read the A/D data registers.)
285
Continuous A/D conversion Set* Clear*
ADST Clear* A/D conversion time Waiting A/D conversion Waiting A/D conversion Waiting A/D conversion Waiting Transfer A/D conversion A/D conversion Waiting Waiting A/D conversion A/D conversion Waiting
ADF
Channel 0 (AN 0 )
Channel 1 (AN 1 )
Waiting
Channel 2 (AN 2 )
Waiting
Figure 15-4 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected)
286
Channel 3 (AN 3 )
ADDRA
ADDRB
A/D conversion
ADDRC
A/D conversion
ADDRD
*
indicates execution of a software instruction
15.5 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time tD after the ADST bit is set to 1. The sampling process lasts for a time tSPL. The actual A/D conversion begins after sampling is completed. Figure 15-5 shows the timing of these steps, and table 15-4 lists the total conversion times (tCONV) for the single mode. The total conversion time includes tD and tSPL. The purpose of tD is to synchronize the ADCSR write time with the A/D conversion process, so the length of tD is variable. The total conversion time therefore varies within the minimum to maximum ranges indicated in table 15-4. In the scan mode, the ranges given in table 15-4 apply to the first conversion. The length of the second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states (when CKS = 1).
287
(1) o
Internal address bus
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV
(1) (2) tD t SPL t CONV
: : : : :
ADCSR write cycle ADCSR address Synchronization delay Input sampling time Total A/D conversion time
Figure 15-5 A/D Conversion Timing Table 15-4 A/D Conversion Time (Single Mode)
CKS = "0" Min Typ Max 18 -- 33 -- 63 -- 259 -- 274 CKS = "1" Min Typ Max 10 -- 17 -- 31 -- 131 -- 138
Item Synchronization delay Input sampling time Total A/D conversion time
Symbol tD tSPL tCONV
Note: Values in the table are numbers of states.
288
15.6 Interrupts and the Data Transfer Controller
The ADI interrupt request is enabled or disabled by the ADIE bit in the ADCSR. When the ADI bit in data transfer enable register DTED (bit 0 at address H'FFF7) is set to 1, the ADI interrupt is served by the data transfer controller. The DTC can be used to transfer A/D results to a buffer in memory, or to an I/O port. The DTC automatically clears the ADF bit to 0. Note: In scan mode, the DTC can transfer data for only one channel per interrupt, even if two or more channels are selected.
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Section 16 RAM
16.1 Overview
The H8/532 includes 1K byte of on-chip static RAM, connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'FB80 to H'FF7F in the chip's address space. A RAM control register (RAMCR) can enable or disable the on-chip RAM, permitting these addresses to be allocated to external memory instead, if so desired. 16.1.1 Block Diagram Figure 16-1 shows the block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits) Address H'FB80 H'FB82 RAMCR
On-chip RAM H'FF7E Even addresses Odd addresses
RAMCR: RAM Control Register
Figure 16-1 Block Diagram of On-Chip RAM
291
16.1.2 Register Configuration The on-chip RAM is controlled by the register described in table 16-1. Table 16-1 RAM Control Register
Name RAM control register Abbreviation RAMCR R/W R/W Initial Value H'FF Address H'FFF9
16.2 RAM Control Register (RAMCR)
Bit 7 RAME Initial value Read/Write 1 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The RAM control register (RAMCR) is an 8-bit register that enables or disable the on-chip RAM. Bit 7--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized on the rising edge of the signal. It is not initialized in the software standby mode.
Bit 7 RAME 0 1
Description On-chip RAM is disabled. On-chip RAM is enabled.
(Initial value)
Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1.
16.3 Operation
16.3.1 Expanded Modes (Modes 1, 2, 3, and 4) If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to addresses H'FB80 to H'FF7F are directed to the external data bus.
292
16.3.2 Single-Chip Mode (Mode 7) If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, access of any type (instruction fetch or data read or write) to addresses H'FB80 to H'FF7F causes an address error and initiates the CPU's exception-handling sequence.
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Section 17 ROM
17.1 Overview
The H8/532 includes 32K bytes of high-speed, on-chip ROM. The on-chip ROM is connected to the CPU via a 16-bit data bus and is accessed in two states. Users wishing to program the chip themselves can request electrically programmable ROM (PROM). The PROM version of the H8/532 has a PROM mode in which the chip can be programmed with a standard, external PROM writer. The chip is also available with masked ROM. The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is determined by the inputs at the mode pins when the chip comes out of the reset state. See table 17-1. Table 17-1 ROM Usage in Each MCU Mode
Mode Pins MD2 MD1 MD0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1
Mode Mode 1 (expanded minimum mode) Mode 2 (expanded minimum mode) Mode 3 (expanded maximum mode) Mode 4 (expanded maximum mode) Mode 7 (single-chip mode)
ROM Disabled (external addresses) Enabled Disabled (external addresses) Enabled Enabled
17.1.1 Block Diagram Figure 17-1 shows the block diagram of the on-chip ROM.
295
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits) Addresses H'0000 H'0002
On-chip ROM H'7FFF Even addresses Odd addresses
Figure 17-1 Block Diagram of On-Chip ROM
17.2 PROM Mode
17.2.1 PROM Mode Setup The PROM version of the H8/532 has a PROM mode in which the usual microcomputer functions are halted to allow the on-chip PROM to be programmed. The programming method is the same as for the HN27C256. To select the PROM mode, apply the signal inputs listed in table 17-2. Table 17-2 Selection of PROM Mode
Pin Mode pins (MD2, MD1, and MD0) STBY pin P61 and P60 Input Low Low High
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17.2.2 Socket Adapter Pin Arrangements and Memory Map The H8/532 can be programmed with a general-purpose PROM writer by attaching a socket adapter as listed in table 17-3. The socket adapter depends on the type of package. Figure 17-2 shows the socket adapter pin arrangements by giving the correspondence between H8/532 pins and HN27C256 pin functions. Figure 17-3 is a memory map. Table 17-3 Socket Adapter
Package 84-Pin PLCC (CP-84) 84-Pin windowed LCC (CG-84) 80-Pin plastic QFP (FP-80A) Socket Adapter HS538ESC01H HS538ESG01H HS538ESH01H
297
H8/532 FP-80A 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 38 39 60 5 42 6 7 8 9 51 12 29 71 -- -- -- CG-84, CP-84 21 RES 22 NMI 25 P30 26 P31 27 P32 28 P33 29 P34 30 P35 31 P36 32 P37 33 P40 34 P41 35 P42 36 P43 37 P44 38 P45 39 P46 40 P47 43 P50 44 P51 45 P52 46 P53 47 P54 48 P55 49 P56 50 P57 51 P60 52 P61 74 AVCC 16 VCC 55 VCC 17 MD0 18 MD1 19 MD2 20 STBY 65 AVss 2 Vss 24 Vss 41 Vss 42 Vss 64 Vss 83 Vss
EPROM socket HN27C256 (28 pins) 1 24 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 22 21 23 2 26 27 20 28
* * * * * * * * * * * * * *
VPP EA9 EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 OE EA10 EA11 EA12 EA13 EA14 CE VCC
Vss
14
VPP: E7 to E0: EA14 to EA0: OE: CE:
Programming power (12.5V) Data input/output Address input Output enable Chip enable
Note: All pins not shown in this figure should be left open.
Figure 17-2 Socket Adapter Pin Arrangements
298
Address in MCU mode H'0000
Address in PROM mode H'0000
On-chip ROM
H'7FFF
H'7FFF
Figure 17-3 Memory Map in PROM Mode
17.3 Programming
The write, verify, and inhibited sub-modes of the PROM mode are selected as shown in table 17-4. Table 17-4 Selection of Sub-Modes in PROM Mode
Pins Mode CE OE VPP VCC 07 to 00 Write Low High VPP VCC Data input Verify High Low VPP VCC Data output VCC High-impedance Programming inhibited High High VPP Note: The VPP and VCC pins must be held at the VPP and VCC voltage levels.
A14 to A0 Address input Address input Address input
The H8/532 PROM uses the same, standard read/write specifications as the HN27C256 and HN27256. 17.3.1 Writing and Verifying An efficient, high-speed programming procedure can be used to write and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. It leaves the data H'FF written in unused addresses.
299
Figure 17-4 shows the basic high-speed programming flowchart. Tables 17-5 and 17-6 list the electrical characteristics of the chip in the PROM mode. Figure 17-5 shows a write/verify timing chart.
START
SET program mode Vcc = 6.0V 0.25V, Vpp = 12.5V 0.3V
Address = 0
n=0
n + 11
Write time tpw = 1 ms 5% Y N S = 25 nN
Verify OK?
Address + 1 Address
Y SET program mode Vcc = 6.0V 0.25V, Vpp = 12.5V 0.3V
Write topw = 3n ms
N Last address? Y SET read mode Vcc = 5.0V 0.5V, Vpp = Vcc
NOGO Error All address read? GO END
Figure 17-4 High-Speed Programming Flowchart
300
Table 17-5 DC Characteristics (When VCC = 6.0V 0.25V, VPP = 12.5V 0.3V, VSS = 0V, Ta = 25C 5C)
SymItem bol Min Input High voltage O7 to O0, A14 to A0, OE, CE VIH 2.4 Input Low voltage O7 to O0, A14 to A0, OE, CE VIL -0.3 VOH 2.4 Input High voltage O7 to O0 Input Low voltage Input leakage current VCC current VPP current VOL -- O7 to O0 O7 to O0, A14 to A0, OE, CE |ILI| -- ICC IPP -- -- Measurement Typ Max Unit Conditions -- VCC + 0.3 V -- 0.8 V ---- V IOH = -200A -- 0.45 V IOL = 1.6mA --2 A Vin = 5.25V/0.5V -- 40 mA -- 40 mA
Table 17-6 AC Characteristics (When VCC = 6.0V 0.25V, VPP = 12.5V 0.3V, Ta = 25C 5C)
Symbol Min 2 tAS tOES 2 tDS 2 tAH 0 tDH 2 tDF -- tVPS 2 tPW 0.95 tOPW 2.85 Measurement Unit Conditions s See figure s 17-5* s s s s s ms ms s ns
Item Typ -- Address setup time OE setup time -- Data setup time -- -- Address hold time Data hold time -- Data output disable time -- -- VPP setup time Program pulse width 1.0 OE pulse width for -- overwrite-programming tVCS 2 -- VCC setup time -- Data output delay time tOE 0 * Input pulse level: 0.8V to 2.2V Input rise/fall time 20ns Timing reference levels: input--1.0V, 2.0V; output--0.8V, 2.0V
Max -- -- -- -- -- 130 -- 1.05 78.75 -- 500
301
Write
Verify
Address
tAS
Data Input data
tAH
Output data
tDS Vpp Vpp Vcc
tDH
tDF
tVPS
Vcc Vcc
GND
tVCS
CE
tPW
OE
tOES
tOE
tOPW
Figure 17-5 PROM Write/Verify Timing 17.3.2 Notes on Writing 1. Write with the specified voltages and timing. The programming voltage (Vpp) in the PROM mode is 12.5V. Caution: Applied voltages in excess of the specified values can permanently destroy to the chip. Be particularly careful about the PROM writer's overshoot characteristics. If the PROM writer is set to Intel specifications or Hitachi HN27256 or HN27C256 specifications, Vpp will be 12.5V. 2. Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM writer, socket adapter, and chip are not correctly aligned.
302
3. Don't touch the socket adapter or chip while writing. Touching either of these can cause contact faults and write errors. 17.3.3 Reliability of Written Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 17-6 shows the recommended screening procedure.
Write program
Bake with power off 150C 48 Hr
Read and check program VCC = 4.5V and 5.5V
Install
Figure 17-6 Recommended Screening Procedure If a series of write errors occur while the same PROM writer is in use, stop programming and check the PROM writer and socket adapter for defects, using a microcomputer with a windowed package and on-chip EPROM. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking.
303
17.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light. Table 17-7 lists the erasing conditions. Table 17-7 Erasing Conditions
Item Ultraviolet wavelength Minimum illumination Value 253.7nm 15W*s/cm2
The conditions in table 17-7 can be satisfied by placing a 12000W/cm2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes.
17.4 Handling of Windowed Packages
1. Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. If the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward. Accumulation of static charge on the window surface can be prevented by the following precautions: (1) When handling the package, ground yourself. Don't wear gloves. Avoid other possible sources of static charge. (2) Avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. (3) Be careful when using cooling sprays, since they may have a slight ion content. (4) Cover the window with an ultraviolet-shield label, preferably a label including a conductive material. Besides protecting the PROM contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. 2. Handling after Programming: Fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert.
304
In addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. It is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 3. 84-Pin LCC Package Mounting: When mounted on a printed circuit board, the 84-pin LCC package must be mounted in a socket. The recommended socket is listed in table 17-8. Table 17-8 Socket for 84-Pin LCC Package
Manufacturer Sumitomo 3-M Product Code 284-1273-00-1102J
305
Section 18 Power-Down State
18.1 Overview
The H8/532 has a power-down state that greatly reduces power consumption by stopping the CPU functions. The power-down state includes three modes: 1. Sleep mode-- a software-triggered mode in which the CPU halts but the rest of the chip remains active 2. Software standby mode-- a software-triggered mode in which the entire chip is inactive 3. Hardware standby mode-- a hardware-triggered mode in which the entire chip is inactive The sleep mode and software standby mode are entered from the program execution state by executing the SLEEP instruction under the conditions given in table 18-1. The hardware standby mode is entered from any other state by a Low input at the STBY pin. Table 18-1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc., in each power-down mode. Table 18-1 Power-Down State
Entering Procedure Execute SLEEP instruction Set SSBY bit in SBYCR to 1, then execute SLEEP instruction* Set STBY pin to Low level CPU Reg's. Held Sup. Mod's. Run I/O Ports Held Exiting Methods * Interrupt * RES Low * STBY Low * NMI * RES Low * STBY Low
Mode Sleep mode Software standby mode
Clock Run
CPU Halt
RAM Held
Halt
Halt
Held
Halt and partly initialized Halt and partly initialized
Held
Held
HardHalt Halt Not ware held standby mode * The watchdog timer must also be stopped. Notes: SBYCR Software standby control register SSBY Software standby bit
Held
High impedance state
* STBY High, then RES Low High
307
18.2 Sleep Mode
18.2.1 Transition to Sleep Mode Execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The functions of the on-chip supporting modules do not stop in the sleep mode. 18.2.2 Exit from Sleep Mode The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a Low input at the RES or STBY pin. 1. Wake-Up by Interrupt: An interrupt releases the sleep mode and starts either the CPU's interrupt-handling sequence or the data transfer controller (DTC). If the interrupt is served by the DTC, after the data transfer is completed the CPU executes the instruction following the SLEEP instruction, unless the count in the data transfer count register (DTCR) is 0. If an interrupt on a level equal to or less than the mask level in the CPU's status register (SR) is requested, the interrupt is left pending and the sleep mode continues. Also, if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. 2. Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to the reset state. 3. Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode to the hardware standby mode.
18.3 Software Standby Mode
18.3.1 Transition to Software Standby Mode A program enters the software standby mode by setting the standby bit (SSBY) in the software standby control register (SBYCR) to 1, then executing the SLEEP instruction. Table 18-2 lists the attributes of the software standby control register.
308
Table 18-2 Software Standby Control Register
Name Software standby control register Abbreviation SBYCR R/W R/W Initial Value H'7F Address H'FFFB
In the software standby mode, the CPU, clock, and the on-chip supporting module functions all stop, reducing power consumption to an extremely low level. The on-chip supporting modules and their registers are reset to their initial state, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents of the CPU registers and on-chip RAM remain unchanged. The I/O ports also remain in their current states. 18.3.2 Software Standby Control Register (SBYCR)
Bit 7 SSBY Initial value Read/Write 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The software standby control register (SBYCR) is an 8-bit register that controls the action of the SLEEP instruction. Bit 7--Software Standby (SSBY): This bit enables or disables the transition to the software standby mode.
Bit 7 SSBY 0 1
Description The SLEEP instruction causes a transition to the sleep mode. (Initial value) The SLEEP instruction causes a transition to the software standby mode.
The watchdog timer must be stopped before the chip can enter the software standby mode. To stop the watchdog timer, clear the timer enable bit (TME) in the watchdog timer's timer control/status register (TCSR) to 0. The SSBY bit cannot be set to 1 while the TME bit is set to 1. When the chip is recovered from the software standby mode by a nonmaskable interrupt (NMI), the SSBY bit is automatically cleared to 0. It is also cleared to 0 by a reset or transition to the hardware standby mode. Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1.
309
18.3.3 Exit from Software Standby Mode The chip can be brought out of the software standby mode by an input at one of three pins: the NMI pin, RES pin, or STBY pin. 1. Recovery by NMI Pin: When an NMI request signal is received, the clock oscillator begins operating but clock pulses are supplied only to the watchdog timer (WDT). The watchdog timer begins counting from H'00 at the rate determined by the clock select bits (CKS2 to CKS0) in its timer status/control register (TCSR). This rate should be set slow enough to allow the clock oscillator to stabilize before the count reaches H'FF. When the count overflows from H'FF to H'00, clock pulses are supplied to the whole chip, the software standby mode ends, and execution of the NMI interrupt-handling sequence begins. The clock select bits (CKS2 to CKS0) should be set as follows. (1) Crystal oscillator: Set CKS2 to CKS0 to a value that makes the watchdog timer interval equal to or greater than 10ms, which is the clock stabilization time. (2) External clock input: CKS2 to CKS0 can be set to any value. The minimum value (CKS2 = CKS1 = CKS0 = 0) is recommended. 2. Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts. Next, when the RES pin goes High, the CPU begins executing the reset sequence. When the chip recovers from the software standby mode by a reset, clock pulses are supplied to the entire chip at once. Be sure to hold the RES pin Low long enough for the clock to stabilize. 3. Recovery by STBY Pin: When STBY the pin goes Low, the chip exits from the software standby mode to the hardware standby mode. 18.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode on the falling edge of the NMI input and recovers from the software standby mode on the rising edge of NMI. Figure 18-1 shows a timing chart of the transitions. The nonmaskable interrupt edge bit (NMIEG) in the port 1 control register (P1CR) is originally cleared to 0, selecting the falling edge as the NMI trigger. After accepting an NMI interrupt in this condition, software changes the NMIEG bit to 1, sets the SSBY bit to 1, and executes the SLEEP instruction to enter the software standby mode. The chip recovers from the software standby mode on the next rising edge at the NMI pin.
310
Oscillator
o
NMI
NMEG
SSBY Clock setting time
NMI interrupt handling NMIEG = 1 SSBY = 1 SLEEP instruction
Software standby mode (Power-down state)
NMI interrupt handling WDT interval (tOSC2 )
Clock start-up time
WDT overflow
Figure 18-1 NMI Timing of Software Standby Mode (Application Example) 18.3.5 Application Notes (1) The I/O ports retain their current states in the software standby mode. If a port is in the High output state, its output current is not reduced in the software standby mode. (2) If the software standby mode is entered under either condition or condition below in a ZTAT version of the H8/532, current dissipation is greater than in normal standby mode (ICC = 100 to 300A). This problem does not occur in H8/532 versions with masked ROM. In single-chip mode (mode 3): if software standby mode is entered after even one instruction not stored in on-chip ROM has been fetched (e.g. from on-chip RAM). In expanded mode with on-chip ROM enabled (mode 2): if software standby mode is entered after even one instruction not stored in on-chip ROM has been fetched (e.g. from external memory or on-chip RAM). This problem does not occur in the expanded mode when on-chip ROM is disabled (mode 1). In applications in which the additional standby current must be avoided, take one of the following actions:
311
* *
Store program code only in on-chip ROM. Use the hardware standby mode. There is never any additional current in hardware standby mode.
18.4 Hardware Standby Mode
18.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes Low. The hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The registers of the on-chip supporting modules are reset to their initial values. Only the on-chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at least 2V).* Notes: 1 2 The RAME bit in the RAM control register should be cleared to 0 before the STBY pin goes Low, to disable the on-chip RAM during the hardware standby mode. Do not change the inputs at the mode pins (MD2, MD1, MD0) during hardware standby mode. Be particularly careful not to let all three mode inputs go low, since that would place the chip in PROM mode, causing increased current dissipation.
18.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low at this time and should be held Low long enough for the clock to stabilize. When the RES pin changes from Low to High, the reset sequence is executed and the chip returns to the program execution state.
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18.4.3 Timing Sequence of Hardware Standby Mode Figure 18-2 shows the usual sequence for entering and leaving the hardware standby mode. First the RES pin goes Low, placing the chip in the reset state. Then the STBY pin goes Low, placing the chip in the hardware standby mode and stopping the clock. In the recovery sequence first the STBY pin goes High; then after the clock stabilizes, the RES pin is returned to the High level.
Oscillator
RES
STBY
Clock setting time Restart
Figure 18-2 Hardware Standby Sequence
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Section 19 E Clock Interface
19.1 Overview
For interfacing to E clock based peripheral devices, the H8/532 can generate an E clock output. Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E clock. The E clock is created by dividing the system clock (o) by 8. The E clock is output at the P11 pin when the P11DDR bit in the port 1 data direction register (P1DDR) is set to 1. When the CPU executes an instruction that synchronizes with the E clock, the address is output on the address bus as usual, but the data bus and the R/W, DS, RD, and WR signal lines do not become active until the falling edge of the E clock is detected. The length of the access cycle for an instruction synchronized with the E clock is accordingly variable. Figures 19-1 and 19-2 show the timing in the cases of maximum and minimum synchronization delay. The wait state controller (WSC) does not insert any wait states (Tw) during the execution of an instruction synchronized with the E clock.
315
Last state
T1
T2
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
T3
o
E
A19 to A0
R/W
Figure 19-1 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Maximum Synchronization Delay)
316
AS,
DS (Read access),
RD
DS (Write access),
WR
D7 to D0 (Read access)
D7 to D0 (Write access)
Last state o
T1
T2
TE
TE
TE
TE
TE
TE
TE
T3
E
A19 to A0
R/W AS, DS (Read access), RD DS (Write access), WR
D7 to D0 (Read access)
D7 to D0 (Write access)
Figure 19-2 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Minimum Synchronization Delay)
317
Section 20 Electrical Specifications
20.1 Absolute Maximum Ratings
Table 20-1 lists the absolute maximum ratings. Table 20-1 Absolute Maximum Ratings
Item Supply voltage Programming voltage Input voltage (except Port 8) (Port 8) Analog supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC VPP Vin Vin AVCC VAN Topr Tstg Rating -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 Unit V V V V V V C C C
Note: Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
20.2 Electrical Characteristics
20.2.1 DC Characteristics Table 20-2 lists the DC characteristics.
319
Table 20-2 DC Characteristics Conditions: VCC = 5.0V 10%*1, AVCC = 5.0V 10%,*1 VSS = AVSS = 0V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
Symbol VIH Measurement Unit Conditions V
Item Input High voltage RES, STBY, MD2, MD1, MD0 EXTAL Port 8 Other input pins (except port 7) Input Low voltage RES, STBY, VIL MD2, MD1, MD0 Other input pins (except port 7) Schmitt trigger Port 7 VTinput voltage VT+ VT+-VTInput leakage RES | Iin | current STBY, NMI, MD2, MD1, MD0 port 8 Leakage current in 3-state (off state) Input pull-up MOS current Output High Voltage Output Low Voltage Input capacitance Port 9, ports 7 to 1 ports 6 and 5 All output pins All output pins Port 4 | ITSI |
Min VCC - 0.7 VCC x 0.7 2.2 2.2 -0.3 -0.3 1.0 2.0 0.4 - - - -
Typ - - - - - - - - - - - - -
Max VCC+0.3
VCC+0.3 V AVCC+0.3 V VCC+0.3 V 0.5 0.8 2.5 3.5 - 10.0 1.0 1.0 1.0 V V V V V A A A A
Vin = 0.5 to VCC-0.5V Vin = 0.5 to AVCC-0.5V Vin = 0.5 to VCC-0.5V Vin = 0V IOH = -200A IOH = -1mA IOL = 1.6mA IOL = 8mA IOL = 10mA Vin = 0 V f = 1MHz Ta = 25C
-IP VOH VOL
50 VCC-0.5 3.5 - - - - - -
- - - - - - - - -
200 - - 0.4 1.0 1.2 60 30 15
A V V V V V pF pF pF
RES Cin NMI All input pins except RES, NMI Note: *1 AVcc must be connected to a power supply line, even when the A/D converter is not used.
320
Table 20-2 DC Characteristics (cont)
Symbol ICC Measurement Conditions f = 6 MHz f = 8 MHz f = 10 MHz f = 6 MHz f = 8 MHz f = 10 MHz Ta 50C Ta > 50C
Item Current dissipation*2 Normal operation
Sleep mode
Standby Analog supply current During A/D conversion While waiting AICC
Min - - - - - - - - -
Typ 20 25 30 12 16 20 0.01 - 1.2
Max 30 40 50 20 25 30 5.0 20 2.0
Unit mA mA mA mA mA mA A A mA
- 0.01 5.0 A RAM standby voltage VRAM 2.0 - - V *2 Current dissipation values assume that VIH min = VCC - 0.5V, VIL max = 0.5V, all output pins are in the no-load state, and all MOS input pull-ups are off.
Table 20-3 Allowable Output Current Sink Values Conditions: VCC = 5.0V 10%, AVCC = 5.0V 10%, VSS = AVSS = 0V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
Item Allowable output Low current sink (per pin) Allowable output Low current sink (total) Symbol IOL IOL Min - - - - Typ - - - - Max 10 2.0 40 80 Unit mA mA mA mA
Allowable output High -IOH - - 2.0 mA current sink (per pin) Allowable output High Total of all output -IOH - - 25 mA current sink (total) pins Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 20-3. In particular, when driving a Darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 20-1 and 20-2.
Port 4 Other output pins Port 4, total of 8 pins Total of all other output pins All output pins
321
H8/532
- - - - - - -- - - - - - - - -- - -------------
H8/532
Vcc
2 k Port
600 Port 4 LED
------------Darlington pair
Figure 20-1 Example of Circuit for Driving a Darlington Transistor Pair
Figure 20-2 Example of Circuit for Driving an LED
20.2.2 AC Characteristics The AC characteristics of the H8/532 chip are listed in three tables. Bus timing parameters are given in table 20-4, control signal timing parameters in table 20-5, and timing parameters of the on-chip supporting modules in table 20-6. Table 20-4 Bus Timing Conditions: VCC = 5.0V 10%, AVCC = 5.0V 10%, o = 0.5 to 10MHz, VSS = 0V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6MHz Min Max 166.7 2000 65 - 65 - - 15 - 15 - 70 30 - - 70 - 70 - 70 200 - 25 - 8MHz Min Max 125 2000 45 - 45 - - 15 - 15 - 65 25 - - 60 - 60 - 60 150 - 20 - 10MHz Min Max 100 2000 35 - 35 - - 15 - 15 - 65 20 - - 40 - 50 - 50 120 - 15 - Measurement Unit Conditions ns See figure 20-4 ns ns ns ns ns ns ns ns ns ns ns
Item Clock cycle time Clock pulse width Low Clock pulse width High Clock rise time Clock fall time Address delay time Address hold time Data strobe delay time 1 Data strobe delay time 2 Data strobe delay time 3 Write data strobe pulse width Address setup time 1
Symbol tcyc tCL tCH tCr tCf tAD tAH tDSD1 tDSD2 tDSD3 tDSWW tAS1
322
Table 20-4 Bus Timing (cont)
6MHz Min Max 105 - 60 - 0 - - 280 - 70 30 - 30 - 40 - 10 - 40 - - 70 - 70 - tBACD1 - 20 - - 0 50 15 15 - - 8MHz 10MHz Min Max Min Max Unit 80 - 65 - ns 50 - 40 - ns 0 - 0 - ns - 190 - 160 ns - 65 - 65 ns 15 - 10 - ns 25 - 20 - ns 40 - 40 - ns 10 - 10 - ns 40 - 40 - ns - 60 - 55 ns - 60 - 55 ns - tBACD1 - tBACD1 ns - 15 - 15 ns - - 0 40 15 15 - - - - 0 30 15 15 - - ns ns ns ns Measurement Conditions See figure 20-4
Item Address setup time 2 Read data setup time Read data hold time Read data access time Write data delay time Write data setup time Write data hold time Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus floating delay time E clock delay time 11 E clock rise time E clock fall time Read data hold time (E clock sync) Write data hold time (E clock sync)
Symbol tAS2 tRDS tRDH tACC tWDD tWDS tWDH tWTS tWTH tBRQS tBACD1 tBACD2 tBZD tED tEr tEf tRDHE tWDHE
See figure 20-5 See figure 20-10
See figure 20-
See figure 20-6
323
Table 20-5 Control Signal Timing Conditions: VCC = 5.0V 10%, AVCC = 5.0V 10%, o = 0.5 to 10MHz, VSS = 0V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6MHz Min Max 200 - 6.0 - 4.0 - 150 10 50 50 10 200 - - - - - - 8MHz 10MHz Measurement Min Max Min Max Unit Conditions 200 - 200 - ns See figure 20-7 6.0 - 6.0 - tcyc 4.0 - 4.0 - tcyc 150 10 50 50 10 200 - - - - - - 150 10 50 50 10 200 - - - - - - ns ns ns ns ns ns See figure 20-8
Item RES setup time RES pulse width Mode programming setup time NMI setup time NMI hold time IRQ0 setup time IRQ1 setup time IRQ1 hold time NMI pulse width (for recovery from software standby mode) Crystal oscillator settling time (reset) Crystal oscillator settling time (software standby)
Symbol tRESS tRESW tMDS tNMIS tNMIH tIRQ0S tIRQ1S tIRQ1H tNMIW
See figure 20-9
tOSC1 tOSC2
20 10
- -
20 10
- -
20 10
- -
ms ms
See figure 20-12 See figure 18-1
324
Table 20-6 Timing Conditions of On-Chip Supporting Modules Conditions: VCC = 5.0V 10%, AVCC = 5.0V 10%, o = 0.5 to 10MHz, VSS = 0V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6MHz Item FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer clock input setup time Timer clock pulse width Timer reset input setup time PWM SCI Timer output delay time Input clock cycle Input clock pulse width Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time Port Output data delay time Input data setup time Input data hold time (Sync) (Async) (Sync) tSCKW tTXD tRXS tRXH tPWD tPRS tPRH Symbol Min Max tFTOD tFTIS tFTCS tFTCWL, tFTCWH tTMOD tTMCS tTMCWL, tTMCWH tTMRS tPWOD tScyc 1.5 50 - 2 4 0.4 - 100 100 - 50 50 - - 100 - - 0.6 100 - - 100 - - 1.5 50 - 2 4 0.4 - 100 100 - 50 50 - - 100 - - 0.6 100 - - 100 - - 1.5 50 - 2 4 0.4 - - - 100 - - 0.6 100 tcyc ns ns tcyc tcyc tScyc ns ns ns ns ns ns See figure 20-13 See figure 20-21 See figure 20-18 See figure 20-19 See figure 20-20 1.5 - 50 - 100 - 1.5 - 50 - 100 - 1.5 - 50 - 100 - tcyc ns ns See figure 20-16 See figure 20-17 - 50 50 100 - - - 50 50 8MHz Min Max 100 - - 10MHz - 50 50 100 - - ns ns ns See figure 20-15 Measurement See figure 20-14 Min Max Unit Conditions
100 - 100 - - 50 50 100 - -
* Measurement Conditions for AC Characteristics
5V
RL H8/532 output pin
C
RH
C = 90 pF: P1, P2, P3, P4,P4, P6 P6 C = 90 pF: P1, P2, P3, P5, P5, = 30 pF: P7, P9P9 = 30 pF: P7, RL L 2.4 kk R = = 2.4 RHH = 12 k R = 12 k Input/output timing reference levels Input/output timing reference levels Low: 0.8V Low: 0.8V High: 2.0V High: 2.0V
Figure 20-3 Output Load Circuit
325
20.2.3 A/D Converter Characteristics Table 20-7 lists the characteristics of the on-chip A/D converter. Table 20-7 A/D Converter Characteristics Conditions: VCC = 5.0V 10%, AVCC = 5.0V 10%, VSS = AVSS = 0V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6MHz Min Typ 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8MHz Min Typ 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10MHz Max Min Typ Max 10 10 10 10 17.25 -- -- 13.8 20 -- -- 20 10 -- -- 10 2.0 -- -- 2.0 2.0 -- -- 2.0 2.0 -- -- 2.0 0.5 -- -- 0.5 2.5 -- -- 2.5
Item Resolution Conversion time Analog input capacitance Allowable signal-source impedance Nonlinearity error Offset error Full-scale error Quantizing error Absolute accuracy
Max 10 23.0 20 10 2.0 2.0 2.0 0.5 2.5
Unit Bits s pF k LSB LSB LSB LSB LSB
20.3 MCU Operational Timing
This section provides the following timing charts: 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.3.7 20.3.8 Bus timing Control Signal Timing Clock Timing I/O Port Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing Pulse Width Modulation Timer Timing Serial Communication InterfaceTiming Figures 20-4 to 20-6 Figures 20-7 to 20-10 Figures 20-11 and 20-12 Figure 20-13 Figures 20-14 and 20-15 Figures 20-16 to 20-18 Figure 20-19 Figure 20-20 and 20-21
326
20.3.1 Bus Timing 1. Basic Bus Cycle (without Wait States) in Expanded Modes
T1 tcyc tCH o tAD A19 to A0 R/W tAS1 AS, DS (Read), RD tACC D7 to D0 (Read) tAS2 DS (Write), WR tWDD tWDS D7 to D0 (Write) tDSD2 tDSD1 tCf tCr tCL
T2
T3
tDSD3 tAH
tRDS
tRDH
tDSD3 tDSWW tAH
tWDH
Figure 20-4 Basic Bus Cycle (without Wait States) in Expanded Modes
327
2. Basic Bus Cycle (with 1 Wait State) in Expanded Modes
T1
T2
TW
T3
o A19 to A0 R/W DS (Read), RD
D7 to D0 (Read) DS (Write), WR
D7 to D0 (Write)
tWTS
tWTH
tWTS
tWTH
WAIT
Figure 20-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes
328
3. Bus Cycle Synchronized with E Clock
o tED E
A19 to A0 R/W tDSD3 AS, DS (Read), RD tRDHE D7 to D0 (Read) tDSD3 DS (Write), WR D7 to D0 (Write) tWDHE tAH tRDS tAH
Figure 20-6 Bus Cycle Synchronized with E Clock
329
20.3.2 Control Signal Timing 1. Reset Input Timing
o tRESS tRESS
RES tMDS MD2 to MD 0 tRESW
Figure 20-7 Reset Input Timing 2. Interrupt Input Timing
o tNMIS NMI tIRQ1S IRQ1 tIRQ0S IRQ0 tIRQ1H tNMIH
Figure 20-8 Interrupt Input Timing 3. NMI Pulse Width
NMI tNMIW
Figure 20-9 NMI Pulse Width (for Recovery from Software Standby Mode)
330
4. Bus Release State Timing
o BREQ (Input)
tBRQS
tBRQS
tBACD1 BACK (Output) tBZD A19 to A0 , R/W, DS, RD, WR, AS
tBACD2
tAD
Figure 20-10 Bus Release State Timing 20.3.3 Clock Timing 1. E Clock Timing
o
tED
E
tED
tEf
tEr
Figure 20-11 E Clock Timing
331
2. Clock Oscillator Stabilization Timing
STBY
tOSC1
tOSC1
Figure 20-12 Clock Oscillator Stabilization Timing
332
RES
VCC
o
20.3.4 I/O Port Timing
Port read/write cycle T1 T2 T3
o tPRS Port 1 to (Input) port 9 Port 1* to (Output) port 9 * Except P1 1 , P10, and P8 7 to P8 0 tPRH
tPWD
Figure 20-13 I/O Port Input/Output Timing
333
20.3.5 16-Bit Free-Running Timer Timing 1. Free-Running Timer Input/Output Timing
o
Free-running timer counter
Compare-match tFTOD
FTOA 1 , FTOB 1 , FTOA 2 , FTOB 2 , FTOA 3 , FTOB 3
tFTIS
FTI 1, FTI 2, FTI 3
Figure 20-14 Free-Running Timer Input/Output Timing
2. External Clock Input Timing for Free-Running Timers
o tFTCS FTCI 1 , FTCI 2 , FTCI3
tFTCWL
tFTCWH
Figure 20-15 External Clock Input Timing for Free-Running Timers
334
20.3.6 8-Bit Timer Timing 1. 8-Bit Timer Output Timing
o
Timer counter
Compare-match tTMOD
TMO
Figure 20-16 8-Bit Timer Output Timing
2. 8-Bit Timer Clock Input Timing
o tTMCS TMCI tTMCWL tTMCWH tTMCS
Figure 20-17 8-Bit Timer Clock Input Timing
3. 8-Bit Timer Reset Input Timing
o tTMRS TMRI
Timer counter
n
H'00
Figure 20-18 8-Bit Timer Reset Input Timing
335
20.3.7 Pulse Width Modulation Timer Timing
o
Timer counter
Compare-match tPWOD
PW1 , PW2 , PW3
Figure 20-19 PWM Timer Output Timing
20.3.8 Serial Communication Interface Timing
tSCKW
tScyc
Figure 20-20 SCI Input Clock Timing
tScyc Serial clock trXD Transmit data tRXS Receive data tRXH
Figure 20-21 SCI Input/Output Timing (Synchronous Mode)
336
Appendix A Instructions
A.1 Instruction Set
Operation Notation Rd Rs Rn (EAd) (EAs) CCR N Z V C CR PC CP SP General register (destination operand) General register (source operand) General register Destination operand Source operand Condition code register N (Negative) flag in CCR Z (Zero) flag in CCR V (Overflow) flag in CCR C (Carry) flag in CCR Control register Program counter Code page register Stack pointer FP #IMM disp + - x / Frame pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Move Swap Logical NOT
Condition Code Notation 0 1 -- Changed after instruction execution Cleared to 0 Set to 1 Value before operation is retained Changed depending on condition
337
Size Mnemonic Operation B/W Data MOV: G (EAs) Rd B/W transfer Rs (EAd) #IMM (EAd) MOV: E #IMM Rd (short format) B MOV: F @ (d: 8, FP) Rd B/W Rs @ (d: 8, FP)(short format) MOV: I #IMM Rd (short format) W MOV: L (@aa: 8) Rd (short format) B/W MOV: S Rs (@aa: 8) (short format) B/W LDM @ SP + Rn (register list) W STM Rn (register list) @ - SP W XCH Rs Rd W SWAP Rd (upper byte) Rd (lower byte) B MOVTPE Rs (EAd) Synchronized with E clock B MOVFPE (EAs) Rd Synchronized with E clock B ArithADD: G Rd + (EAs) Rd B/W metic ADD: Q (EAd) + #IMM (EAd) B/W opera(#IMM = 1, 2) (short format) tions ADDS Rd + (EAs) Rd B/W (Rd is always word size) ADDX Rd + (EAs) + C Rd B/W B DADD (Rd)10 + (Rs)10 + C (Rd)10 SUB Rd - (EAs) Rd B/W SUBS Rd - (EAs) Rd B/W SUBX Rd - (EAs) - C Rd B/W DSUB (Rd)10 - (Rs)10 - C (Rd)10 B MULXU Rd x (EAs) Rd 8 x 8 B/W (Unsigned) 16 x 16 DIVXU Rd / (EAs) Rd 16 / 8 B/W (Unsigned) 32 / 16 CMP: G Rd - (EAs), Set CCR B/W (EAd) - #IMM, Set CCR CMP: E Rd - #IMM, Set CCR (short format) B CMP: I Rd - #IMM, Set CCR (short format) W
N
CCR Bit ZV 0
C --
-- -- -- -- -- -- -- -- --
-- -- -- -- --
0 0 0 0 0 -- -- -- 0 -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- 0 0
---- -- -- -- -- 0
338
Arithmetic operations
Shift operations
Mnemonic Operation EXTS (< Bit 7 > of < Rd >) (< Bit 15 to 8 > of < Rd >) EXTU 0 ( of < Rd >) TST (EAd) - 0, Set CCR NEG 0 - (EAd) (EAd) CLR 0 (EAd) TAS (EAd) - 0, Set CCR (1)2 (< Bit 7 > of < EAd >) SHAL MSB LSB
C 0 MSB LSB C
Size B/W B B B/W B/W B/W B B/W B/W B/W
0
N 0 0 0 -- -- -- --
CCR Bit ZV 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- --
C 0 0 0 0 0 -- -- -- -- -- -- -- --
SHAR SHLL SHLR
0
MSB C
LSB
MSB
LSB C
B/W B/W B/W
C
ROTL
C
MSB
LSB
ROTR ROTXL ROTXR Logic operations AND OR XOR NOT BSET
MSB
LSB
MSB C
LSB
B/W B/W
C
MSB
LSB
Bit manipulations BCLR BTST BNOT
Rd (EAs) Rd Rd (EAs) Rd Rd (EAs) Rd (EAd) (EAd) (< Bit number > of < EAd >) Z 1 (< Bit number > of < EAd >) (< Bit number > of < EAd >) Z 0 (< Bit number > of < EAd >) (< Bit number > of < EAd >) Z (< Bit number > of < EAd >) Z (< Bit number > of < EAd >)
B/W B/W B/W B/W B/W B/W B/W B/W
339
Mnemonic Operation Branch- Bcc If condition is true then ing PC + disp PC instrucelse next; Mnemonic Description tions
BRA BRN BHI BLS Bcc BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE (BT) (BF) Always (True) Never (False) HIgh Low or Same Carry Clear (High or Same) Carry Set (LOw) Not Equal EQual oVerflow Clear oVerflow Set PLus MInus Greater or Equal Less Than Greater Than Less or Equal
Size B/W --
N --
CCR Bit ZVC ------
(BHS) (BLO)
Condition True False CZ=0 CZ=0 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
Effective address PC Effective address CP, PC PC @ - SP PC + disp PC JSR PC @ - SP Effective address PC PJSR PC @ - SP CP @ - SP Effective address CP, PC RTS @ SP + PC PRTS @ SP + CP @ SP + PC RTD @ SP + PC SP + #IMM SP PRTD @ SP + CP @ SP + PC SP + #IMM SP SCB If condition is true then next; SCB/F else Rn - 1 Rn; SCB/NE If Rn = -1 then next; SCB/EQ else PC + disp PC; JMP PJMP BSR
Mnemonic SCB/F SCB/NE SCB/EQ Description Not Equal Equal Condition False Z=0 Z=1
-- -- -- -- --
-- -- -- -- --
------ ------ ------ ---- ---- -- --
-- -- -- --
-- -- -- --
------ ------ ---- ---- -- --
--
--
----
--
340
Mnemonic Operation System TRAPA PC @ - SP control (If MAX MODE CP @ - SP) SR @ - SP (If MAX MODE < vector > CP) < vector > PC TRAP/VS If V bit = "1" then TRAP else next; RTE @ SP + SR (If MAX MODE @ SP + CP) @ SP + PC LINK FP (R6) @ - SP SP FP (R6) SP + #IMM SP UNLK FP (R6) SP @SP + FP Normal running mode power-down state SLEEP LDC (EAs) CR STC CR (EAd) ANDC CR #IMM CR ORC CR #IMM CR XORC CR #IMM CR NOP PC + 1 PC * Depends on the CR.
Size B/W --
N --
CCR Bit ZV ----
C --
-- --
--
--
--
--
--
--
--
--
--
-- -- B/W* B/W* B/W* B/W* B/W* --
-- -- --
-- -- --
-- -- --
-- -- --
--
--
--
--
341
A.2 Instruction Codes
Table A-1 shows the machine-language coding of each instruction. * How to read table A-1 (a) to (d) The general operand format consists of an effective address (EA) field and operation-code (OP) field specified in the following order.
EA field Op field
1
2
3
4
5
6
Bytes 2, 3, 5, 6 are not present in all instructions.
342
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
disp (L)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
3
@Rn
Instruction Rn MOV:G.B , Rd Instruction MOV:G.W , Rd MOV:G.B Rs , MOV:G.W Rs , 2 2
#xx:8
Operation code (OP) 4 1 0 0 0 0 r d r d rd 5 6
2 2 2 2
3 3 3 3
4 4 4 4
2 2 2 2
2 2 2 2
3 3 3 3
4 4 4 4
3
4 1 0 0 0 0 r d r d rd 3 1 0 0 1 0 r s r s rs 4 1 0 0 1 0 r s r s rs Shading indicates addressing modes not available for this instruction.
Byte length of instruction
Some instructions have a special format in which the operation code comes first.
The following notation is used in the tables.
* Sz:
Operand size (byte or word)
Byte: Sz = 0 Word: Sz = 1
343
* rrr : General register number field
rrr 15 000 001 010 011 100 101 110 111
Sz = 0 (Byte) 87 Not used Not used Not used Not used Not used Not used Not used Not used R0 R1 R2 R3 R4 R5 R6 R7 0 15
Sz = 1 (Word) 0 R0 R1 R2 R3 R4 R5 R6 R7
* ccc : Control register number field
ccc 000 7 001 010 011 100 101 110 111
Sz = 0 (Byte) (Not allowed*) 0 CCR (Not allowed) BR EP DP (Not allowed) TP 15
Sz = 1 (Word) 0 SR (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed)
* "Disallowed" means that this combination of bits must not be specified. Specifying a disallowed combination may cause abnormal results.
344
* register list: A byte in which bits indicate general registers as follows
Bit 7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
* #VEC: Four bits designating a vector number from 0 to 15. The vector numbers correspond to addresses of entries in the exception vector table as follows:
Vector Address #VEC Minimum Mode Maximum Mode 0 H'0020 - H'0021 H'0040 - H'0043 1 H'0022 - H'0023 H'0044 - H'0047 2 H'0024 - H'0025 H'0048 - H'004B 3 H'0026 - H'0027 H'004C - H'004F 4 H'0028 - H'0029 H'0050 - H'0053 5 H'002A - H'002B H'0054 - H'0057 6 H'002C - H'002D H'0058 - H'005B 7 H'002E - H'002F H'005C - H'005F Vector Address #VEC Minimum Mode Maximum Mode 8 H'0030 - H'0031 H'0060 - H'0063 9 H'0032 - H'0033 H'0064 - H'0067 10 H'0034 - H'0035 H'0068 - H'006B 11 H'0036 - H'0037 H'006C - H'006F 12 H'0038 - H'0039 H'0070 - H'0073 13 H'003A - H'003B H'0074 - H'0077 14 H'003C - H'003D H'0078 - H'007B 15 H'003E - H'003F H'007C - H'007F
* Examples of machine-language coding Example 1: ADD:G.B @R0, R1
Table A-1 (a) Machine code EA Field OP Field 1101Szrrr 00100rdrdrd 11010000 00100 0 0 1 H'D021
Example 2: ADD:G.W @H'11:8, R1
Table A-1 (a) Machine code EA Field 0000Sz101 00010001 0000 1 101 00010001 H'0D1121 OP Field 00100rdrdrd 00100 0 0 1
345
Table A-1 (a) Machine Language Coding [General Format]
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn MOV:G.B , Rd MOV:G.W , Rd MOV:G.B Rs , Data transfer instruction MOV:G.W Rs , MOV:G.B #xx:8, MOV:G.W #xx:8, MOV:G.W #xx:16, LDM.W @SP+, XCH.W Rs ,Rd SWAP.B Rd MOVTPE.B Rs , MOVTPE.B , R d ADD:G.B , Rd ADD:G.W , Rd Arithmetic operation instruction ADD:Q.B #1, * ADD:Q.W #1, * ADD:Q.B #2, * ADD:Q.W #2, * ADD:Q.B #-1, * ADD:Q.W #-1, * ADD:Q.B #-2, * ADD:Q.W #-2, * ADDS.B , Rd ADDS.W , Rd ADDX.B , Rd ADDX.W , Rd Note: * Short format instruction 2 2 2 2 2 2 2 2 2 2 2 2 2 2

#xx:8
Operation code (OP) 4 1 0 0 0 0 rd rd rd 5 6
2 2
2 2 2 2 3 3 4
3 3 3 3 4 4 5
4 4 4 4 5 5 6
2 2 2 2 3 3 4 2
2 2 2 2 3 3 4 2
3 3 3 3 4 4 5
4 4 4 4 5 5 6
3
4 1 0 0 0 0 rd rd rd 1 0 0 1 0 rs rs rs 4 1 0 0 1 0 rs rs rs 0 0 0 0 0 1 1 0 data 0 0 0 0 0 1 1 0 data 0 0 0 0 0 1 1 1 data (H) 0 0 0 0 0 0 1 0 register list 0 0 0 0 0 0 1 0 register list 1 0 0 1 0 rd rd rd 00010000 data (L)
STM.W ,@-SP 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4
3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3
5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3
0 0 0 0 0 0 0 0 1 0 0 1 0 rs rs rs 0 0 0 0 0 0 0 0 1 0 0 1 0 rd rd rd 0 0 1 0 0 rd rd rd 4 0 0 1 0 0 rd rd rd 00001000 00001000 00001001 00001001 00001100 00001100 00001101 00001101 0 0 1 0 1 rd rd rd 4 0 0 1 0 1 rd rd rd 1 0 1 0 0 rd rd rd 4 1 0 1 0 0 rd rd rd
346
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn DADD.B Rs ,Rd SUB.B , R d SUB.W , R d SUBS.B , R d SUBS.W ,Rd SUBX.B , Rd SUBX.W , R d DSUB.B R s , R d Arithmetic operation instruction MULXU.B , R d MULXU.X , R d DIVXU.B , Rd DIVXU.W , R d CMP:G.B , R d CMP:G.W , R d CMP:G.B #xx, CMP:G.W #xx, EXTS.B Rd EXTU.B Rd TST.B TST.W NEG.B NEG.W CLR.B CLR.W TAS.B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 0 0 1 1 0 rd rd rd 5 6
0 0 0 0 0 0 0 0 1 0 1 0 0 rd rd rd 2 2 2 2 2 2 2 2 2 2 3 2 3 4 3 3 3 3 3 3 3 3 3 3 4 3 4 5 4 4 4 4 4 4 4 4 4 4 5 4 5 6 2 2 2 2 2 2 2 2 2 2 3 2 3 4 2 2 2 2 2 2 2 2 2 2 3 2 3 4 3 3 3 3 3 3 3 3 3 3 4 3 4 5 4 4 4 4 4 4 4 4 4 4 5 4 5 6 3 3 3 3 3 3 4 0 0 1 1 0 rd rd rd 0 0 1 1 1 rd rd rd 4 0 0 1 1 1 rd rd rd 1 0 1 1 0 rd rd rd 4 1 0 1 1 0 rd rd rd 0 0 0 0 0 0 0 0 1 0 1 1 0 rd rd rd 1 0 1 0 1 rd rd rd 4 1 0 1 0 1 rd rd rd 1 0 1 1 1 rd rd rd 4 1 0 1 1 1 rd rd rd 0 1 1 1 0 rd rd rd 4 0 1 1 1 0 rd rd rd 0 0 0 0 0 1 0 0 data 0 0 0 0 0 1 0 1 data (H) 00010001 00010010 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 00010110 00010110 00010100 00010100 00010011 00010011 00010111 data (L)
347
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn SHAL.B SHAL.W SHAR.B SHAR.W SHLL.B SHLL.W Shift instruction SHLR.B SHLR.W ROTL.B ROTL.W ROTR.B ROTR.W ROTXL.B ROTXL.W ROTXR.B ROTXR.W Logic operation instruction AND.B , Rd AND.W , Rd OR.B.B , Rd OR.B.W , Rd XOR.B , Rd XOR.W , Rd NOT.B NOT.W 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 00011000 00011000 00011001 00011001 00011010 00011010 00011011 00011011 00011100 00011100 00011101 00011101 00011110 00011110 00011111 00011111 5 6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3
0 1 0 1 0 rd rd rd 4 0 1 0 1 0 rd rd rd 0 1 0 0 0 rd rd rd 4 0 1 0 0 0 rd rd rd 0 1 1 0 0 rd rd rd 4 0 1 1 0 0 rd rd rd 00010101 00010101
348
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn BSET.B #xx, BSET.W #xx, BSET.B R s , BSET.W Rs , Bit manipulate instruction BCLR.B #xx, BCLR.W #xx, BCLR.B R s , BCLR.W Rs , BTST.B #xx, BTST.W #xx, BTST.B Rs , BTST.W Rs , BNOT.B #xx, BNOT.W #xx, BNOT.B R s , BNOT.W Rs , LDC.B , CR System control instruction LDC.W , CR STC.B CR, STC.W CR, ANDC.B #xx:8, CR ANDC.W #xx:16, CR ORC.B #xx:8, CR ORC.W #xx:16, CR XORC.B #xx:8, CR XORC.W #xx:16, CR 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 1 1 0 0 (data) 1 1 0 0 (data) 0 1 0 0 1 rs rs rs 0 1 0 0 1 rs rs rs 1 1 0 1 (data) 1 1 0 1 (data) 0 1 0 1 1 rs rs rs 0 1 0 1 1 rs rs rs 1 1 1 1 (data) 1 1 1 1 (data) 0 1 1 1 1 rs rs rs 0 1 1 1 1 rs rs rs 1 1 1 0 (data) 1 1 1 0 (data) 0 1 1 0 1 rs rs rs 0 1 1 0 1 rs rs rs 5 6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3
10001ccc 4 10001ccc 10011ccc 10011ccc 01011ccc 4 01011ccc 01001ccc 4 01001ccc 01101ccc 4 01101ccc
349
Table A-1 (b) Machine Language Coding [Special Format: Short Format]
Instruction MOV:E,B #xx:8,Rd MOV:I.W #xx:16,Rd MOV:L.B @aa:8,Rd MOV:L.W @aa:8,Rd MOV:S.B Rs,@aa:8 MOV:S.W Rs,@aa:8 MOV:F.B @(d:8,R6),Rd MOV:F.W @(d:8,R6),Rd MOV:F.B Rs @(d:8,R6) MOV:F.W Rs,@(d:8,R6) CMP:E.B #xx:8,Rd CMP:I.W #xx:16,Rd Byte 2 3 2 2 2 2 2 2 2 2 2 3 Operation code 2 3 data data (H) address (L) address (L) address (L) address (L) disp disp disp disp data data (H) data (L)
1 01010rdrdrd 01011rdrdrd 01100rdrdrd 01101rdrdrd 01110rsrsrs 01111rsrsrs 10000rdrdrd 10001rdrdrd 10010rsrsrs 10011rsrsrs 01000rdrdrd 01001rdrdrd
4
data (L)
350
Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction]
Instruction Bcc d:8 BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Byte 2 Operation code 2 3 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) 11010rrr address (H)
Bcc d:16
3
JMP @Rn JMP @aa:16
2 3
1 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 00010001 00010000
4
disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) address (L)
351
Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction]
Instruction JMP @(d:8,Rn) JMP @(d:16,Rn) BSR d:8 BSR d:16 JSR @Rn JSR @aa:16 JSR @(d:8,Rn) JSR @(d:16,Rn) RTS RTD #xx:8 RTD #xx:16 SCB/cc Rn,disp SCB/F SCB/NE SCB/EQ PJMP @aa:24 PJMP @Rn PJSR @aa:24 PJSR @Rn PRTS PRTD #xx:8 PRTD #xx:16 Byte 3 4 2 3 2 3 3 4 1 2 3 3 Operation code 2 3 11100rrr disp 11110rrr disp (H) disp disp (H) disp (L) 11011rrr address (H) address (L) 11101rrr disp 11111rrr disp (H) data data (H) 10111rrr 10111rrr 10111rrr page 11000rrr page 11001rrr 00011001 00010100 00011100
4 2 4 2 2 3 4
1 00010001 00010001 00001110 00011110 00010001 00011000 00010001 00010001 00011001 00010100 00011100 00000001 00000110 00000111 00010011 00010001 00000011 00010001 00010001 00010001 00010001
4 disp (L)
disp (L)
data (L) disp disp disp address (H) address (H)
address (L) address (L)
data data (H)
data (L)
Table A-1 (d) Machine Language Coding [Special Format: System Control Instructions]
Instruction TRAPA #xx TRAP/VS RTE LINK FP,#xx:8 LINK FP,#xx:16 UNLK FP SLEEP NOP Byte 2 1 1 2 3 1 1 1 Operation code 2 3 0001 #VEC
1 00001000 00001001 00001010 00010111 00011111 00001111 00011010 00000000
4
data data (H)
data (L)
352
A.3 Operation Code Map
Tables A-2 through A-6 are maps of the operation codes. Table A-2 shows the meaning of the first byte of the instruction code, indicating both operation codes and addressing modes. Tables A-2 through A-6 indicate the meanings of operation codes in the second and third bytes.
Table A-2 Operation Codes in Byte 1
LO A RTE B F UNLK
HI
0 NOP
2 LDM
0
3 PJSR @aa:24
6 SCB/NE See Tbl. A-6 SLEEP
E BSR d:8
JMP
STM
1
PJMP @aa:24
4 #xx:8 See Tbl. A-5 RTD #xx:8
7 8 9 SCB/EQ TRAPA TRAP/V S See Tbl. A-6 LINK JSR RTS #xx:8
BSR d:16
LINK #xx:16
2 BLS Bcc BCS BNE BEQ BVC BVS
1 SCB/F See Tbl. A-6 See Tbl. A-6 * BRN BLS Bcc BNE BEQ BVC BVS BPL BPL BMI BMI
BHI
5 #aa:8.B See Tbl. A-4 @aa:16.B See Tbl. A-4 BCS
C D #xx:16 @aa:8.W See See Tbl. Tbl. A-5 A-4 @aa:16.W RTD #xx:16 See Tbl. A-4 BLT BGE BGE BLT
BGT BGT
BLE BLE
353
R5 R6 R7 R0 R1 (Byte) (Byte) (Byte) (Byte) (Byte) (Byte) See Table A-3 See Table A-4 See Table A-4 See Table A-4 See Table A-4 See Table A-4
3
BRA d:8 BRA d:16
BRN
BHI
4 5 6 7 8 9 A B C D E F
R0
R1
CMP:E #xx:8, Rn R2 R3 R4 MOV:E #xx:8, Rn MOV:L.B @aa:8, Rn MOV:S.B Rn, @aa:8 MOV:F.B @ (d:8, R6), Rn MOV:F.B Rn, @ (d:8, R6) Rn @-Rn @Rn+ @Rn @(d:8,Rn) @(d:16,Rn)
CMP:I #xx:16, Rn R2 R3 R4 R5 MOV:I #xx:16, Rn MOV:L.W @aa:8, Rn MOV:S.W Rn, @aa:8 MOV:F.W @ (:8, R6), Rn MOV:F.W Rn, @ (d:8,R6) (Word) Rn (Word) @-Rn (Word) @Rn+ (Word) @Rn (Word) @(d:8,Rn) (Word) @(d:16,Rn)
R6
R7
See Table A-3 See Table A-4 See Table A-4 See Table A-4 See Table A-4 See Table A-4
Notes: References to tables A-3 through A-6 indicate that the instruction code has one or more additional bytes, described in those tables. * H'11 is the first operation code byte of the following instructions: JMP,JSR, PJSR (register indirect addressing mode) JMP,JSR (register indirect addressing mode with displacement) PRTS, PRTD (all addressing modes)
Table A-3 Operation Codes in Byte 2 (Axxx)
LO 3 ADD:Q #1 ADD:Q #-2 ROTR R5 ROTXL R6 ROTXR R7 CLR ADD R3 R4 SUBS BSET (Register indirect specification of bit number) BCLR (Register indirect specification of bit number) BNOT (Register indirect specification of bit number) BTST (Register indirect specification of bit number) LDC STC MULXU DIVXU R5 R6 R7 R0 R1 R3 R4 SUB OR AND XOR CMP MOV XCH ADDX SUBX ADDS R2 NEG NOT TST TAS SHAL SHAR SHLL SHLR ROTL ADD:Q #2 ADD:Q #-1 4 5 6 7 8 9 A B C D E F
HI
1
2
0
0 See Tbl. A-6*
1
SWAP
EXTS
EXTU
2
R0
R1
R2
3
4
5
6
7
354
b3 b4 b5
8
9
A
B
C
b0
b1
b2
BSET (Immediate specification of bit number) b6 b7 b8 b9 b10 BCLR (Immediate specification of bit number) BNOT (Immediate specification of bit number) BTST (Immediate specification of bit number)
b11
b12
b13
b14
b15
D
E
F
Note: * The operation code is in byte 3, given in table A-6.
Table A-4 Operation Codes in Byte 2 (05xx, 15xx, 0Dxx, 1Dxx, Bxxx, Cxxx, Dxxx, Exxx, Fxxx)
3 CMP #xx:8 CLR ADD SUB OR AND XOR CMP MOV (load) LDC STC MULXU DIVXU BSET (Immediate specification of bit number) BCLR (Immediate specification of bit number) BNOT (Immediate specification of bit number) BTST (Immediate specification of bit number) MOV (store) ADDX SUBX SUBS BSET (Register indirect specification of bit number) BCLR (Register indirect specification of bit number) BNOT (Register indirect specification of bit number) BTST (Register indirect specification of bit number) ADDS NEG NOT TST TAS SHAL SHAR SHLL SHLR ROTL ROTR CMP #xx:16 MOV #xx:8 MOV #xx:16 ADD:Q #1 ADD:Q #2 ADD:Q #-1 ADD:Q #-2 ROTXL ROTXR 4 5 6 7 8 9 A B C D E F
LO
HI
1
2
0
0 See Tbl. A-6*
1
2
3
4
5
6
7
8
355
9
A
B
C
D
E
F
Note: * The operation code is in byte 3, given in table A-6.
Table A-5 Operation Codes in Byte 2 (04xx, 0Cxx)
LO 3 4 5 6 7 8 9 A B C D E F
HI 0
0
1
2
1 ADD SUB OR AND XOR CMP MOV LDC XORC ANDC ORC SUBS ADDS
2
3
4
5
6
7
8
9 ADDX SUBX MULXU DIVXU
356
A
B
C
D
E
F
Table A-6 Operation Codes in Bytes 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx)
LO 3 4 5 6 7 8 9 A B C D E F
HI PRTS
0
1
2
0 PRTD #xx:8 PRTD #xx:16
1
2
3
4
5
6
7
357
R5 R6 R7 MOVTPE DADD DSUB PJMP @Rn JMP @Rn JMP @(d:8,Rn) JMP @(d:16,Rn) R0
8
R0
R1
R2
MOVFPE R3 R4
9
A
B
R1
SCB R2
R3 PJSR @Rn JSR @Rn JSR @(d:8,Rn) JSR @(d:16,Rn)
R4
R5
R6
R7
C
D
E
F
A.4 Instruction Execution Cycles
Tables A-7 (1) through (6) list the number of cycles required by the CPU to execute each instruction in each addressing mode. The meaning of the symbols in the tables is explained below. The values of I, J, and K are used to calculate the number of execution cycles when off-chip memory is accessed for an instruction fetch or operand read/write. The formulas for these calculations are given next. A.4.1 Calculation of Instruction Execution States
Instruction Fetch On-chip memory *1 Operand Read/Write On-chip memory On-chip memory module or off-chip memory *2 Number of States (Value given in table A-7) + (Value in table A-8) Byte (Value in table A-7) + (Value in table A-8) + I Word ((Value in table A-7) + (Value in table A-8) + 2I (Value given in table A-7) + 2(J + K) Byte (Value in table A-7) + I + 2(J + K) Word ((Value in table A-7) + 2(I + J + K)
Off-chip memory *2
On-chip memory On-chip supporting module or off-chip memory *2
Notes: *1. When the instruction is fetched from on-chip memory (ROM or RAM), the number of execution states varies by 1 or 2 depending of whether the instruction is stored at an even or odd address. This difference must be noted when software is used for timing, and in other cases in which the exact number of states is important. *2. If wait states are inserted in access to external memory, add the necessary number of cycles.
358
A.4.2 Tables of Instruction Execution Cycles Tables A-7 (1) through (6) should be read as shown below:
J + K: Number of instruction fetch cycles. Addressing mode @(d:16, Rn) @(d:8, Rn) I: Total number of bytes written and read when operand is in memory. Rn
@aa:16
@aa:8
Instruction ADD.B ADD.W ADD:Q.B ADD:Q.W DADD
1 1 2 2 4
J 1 1 1 1 2
K
1 2 2 2 2 4
1 5 5 7 7
2 5 5 7 7
3 6 6 8 8
1 5 5 7 7
1 6 6 8 8
2 5 5 7 7
3 6 6 8 8
2 3
Shading in the I column means the operand cannot be in memory.
Shading indicates addressing modes that cannot be used with this instruction.
359
#xx:16 3 4
@Rn+
@-Rn
#xx:8
@Rn
* Examples of Calculation of Number of States Required for Execution (Example 1) Instruction fetch from on-chip memory
Operand Read/Write On-chip memory or general register Start Addr. Even Odd Assembler Notation Address Code Mnemonic H'0100 H'D821 ADD @R0, R1 H'0101 H'D821 ADD @R0, R1 Table A-7 + Table A-8 5+1 5+0 Number of States 6 5
(Example 2) Instruction fetch from on-chip memory
Operand Read/Write On-chip supporting module or external memory (word) Start Addr. Even Odd Assembler Notation Address Code Mnemonic H'FC00 H'11D8 JSR @R0 H'FC01 H'11D8 JSR @R0 Table A-7 + Table A-8 + 2I 9+0+2x2 9+1+2x2 Number of States 13 14
(Example 3) Instruction fetch from external memory
Operand Read/Write On-chip memory or general register Assembler Notation Address Code Mnemonic H'9002 H'D821 ADD @R0, R1 Table A-7 + 2(J + K) 5 + 2 x (1 + 1) Number of States 9
360
Table A-7 Instruction Execution Cycles (1)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction ADD:G.B ADD:G.W ADD:Q.B ADD:Q.W ADDS.B ADDS.W ADDX.B ADDX.W AND.B AND.W ANDC BCLR.B BCLR.W BNOT.B BNOT.W BSET.B BSET.W BTST.B BTST.W CLR.B CLR.W CMP:G.B CMP:G.W CMP:G.B #XX:8, CMP:G.B #XX:16,
1 1 2 2 4 1 2 1 2 1 2
J 1 1 1 1 1 1 1 1 1 1 1
K
1 2 2 2 2 3 3 2 2 2 2
1 5 5 7 7 5 5 5 5 5 5
2 5 5 7 7 5 5 5 5 5 5
3 6 6 8 8 6 6 6 6 6 6
1 5 5 7 7 5 5 5 5 5 5
1 6 6 8 8 6 6 6 6 6 6
2 5 5 7 7 5 5 5 5 5 5
3 6 6 8 8 6 6 6 6 6 6
2 3
3 4 3 4 3 4 5 9
2 4 2 4 2 4 1 2 1 2 1 2 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 3
4 4 4 4 4 4 3 3 2 2 2 2
7 7 7 7 7 7 5 5 5 5 5 5 6 7
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8 3 4
361
#xx:16 3 4
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (2)
Addressing mode @(d:8,Rn) Rn) @(d:8, Addressing mode @aa:16 @aa:16 @aa:8 @aa:8 #xx:8 #xx:8 2 2 2 2 4 20 4 26 20 4 26 3 4 3 3 33 4 3 2 4 2 2 2 23 29 23 29 23 24 23 24 23 29 23 29 24 30 24 30 21 21 28 28 4 4 3 3 6 6 4 4 2 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 3 #xx:16 #xx:16 3 3 3 3 29 30 29 30 23 24 23 24 29 30 29 30 @Rn+ @Rn+ @-Rn@-Rn 1 @(d:16,Rn) Rn) @(d:16, 3
J J
CMP:E #xx:8, R d Instruction CMP:I #xx:16, Rd CMP:E #xx:8,Rd DADD CMP:I #xx:16,Rd DIVXU.B DADD DIVXU.W DIVXU.B DSUB DIVXU.W EXTS DSUB EXTU EXTS LDC.B EXTU LDC.W LDC.B MOV.B LDC.W MOV.W MOV.B MOV.B #xx:8, MOV.W MOV.B #xx:16, MOV.B #xx:8, MOV:E #xx:8, Rd MOV.W #xx:16, MOV:I #xx:8, Rd MOV:E #xx:8,Rd MOV:L.B @aa:8, Rd MOV:I #xx:16,Rd MOV:L.W @aa:8, Rd MOV:L.B @aa:8,Rd MOV:S.B Rd ,@aa:8 MOV:L.W @aa:8,Rd MOV:S.W Rd ,@aa:8 MOV:S.B Rs,@aa:8 MOV:F.B @(d:8, R6), Rd MOV:S.W Rs,@aa:8 MOV:F.W @(d:8, R6), Rd MOV:F.B @(d:8, R6), Rd MOV:F.B R d , @(d:8, Rd MOV:F.W @(d:8, R6),R6) MOV:F.W Rd , @(d:8, R6) MOV:F.B Rs, @(d:8, R6) MOV:F.W Rs, @(d:8, R6)
I
0K 0 0 2 0 1 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 2 1 3 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rn
Instruction
1
K
1
@Rn @Rn 1
Rn
2
1
2
3
1
1
2
3
1
1
2
3
1 2 1 2
1 2 1 1 2 2 1 1 2 2 1 2 1 2 1 1 2 2 1 1 2 2 1 1 2 2 1 2
6 7 6 5 7 5 5 7 5 8 7 8
6 7 6 5 7 5 5 7 5 8 7 8
7 8 7 6 8 6 6 8 6 9 8 9
6 7 6 5 7 5 5 7 5 8 7 8
7 8 7 6 8 66 8 6 9 8 9
6 7 6 5 7 5 5 7 5 8 7 8
7 8 7 6 8 6 6 8 6 9 8 9
362
Table A-7 Instruction Execution Cycles (3)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction MOVFPE *
1 0
J 2
K
1
1 13 | 20 13 | 20
2 13 | 20 13 | 20 19 25 7 7 7 7 5 5
3 14 | 21 14 | 21 20 26 8 8 8 8 6 6
1 13 | 20
1 14 | 21
2 13 | 20 13 | 20 19 25 7 7 7 7 5 5
3 14 | 21 14 | 21 20 26 8 8 8 8 6 6
2
MOVTPE *
0
2
13 14 | | 20 21 19 20 25 26 7 7 7 7 5 5 8 8 8 8 6 6
MULXU.B MULXU.W NEG.B NEG.W NOT.B NOT.W OR.B OR.W ORC ROTL.B ROTL.W ROTR.B ROTR.W ROTXL.B ROTXL.W ROTXR.B ROTXR.W SHAL.B SHAL.W SHAR.B SHAR.W SHLL.B SHLL.W
1 2 2 4 2 4 1 2
1 1 1 1 1 1 1 1 1
16 23 2 2 2 2 2 2
19 25 7 7 7 7 5 5
18 25
3 4 5 9
2 4 2 4 2 4 2 4 2 4 2 4 2 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 3 2 2 2 2 2 2 2 2
7 7 7 7 7 7 7 7 7 7 7 7 7 7
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
* MOVFPE and MOVTPE are executed synchronous with the E-clock, so the number of execution states will change depending on timing of the execution.
363
#xx:16 3
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (4)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction SHLR.B SHLR.W STC.B STC.W SUB.B SUB.W SUBS.B SUBS.W SUBX.B SUBX.W SWAP TAS TST.B TST.W XCH XOR.B XOR.W XORC * DIVXU.B DIVXU.B DIVXU.W DIVXU.W DIVXU.B DIVXU.W * Zero divide, minimum mode Zero divide, maximum mode Zero divide, minimum mode Zero divide, maximum mode Overflow Overflow
1 2 4 1 2 1 2 1 2 1 2
J 1 1 1 1 1 1 1 1 1 1 1
K
1 2 2 2 2 2 2 3 3 2 2 3 4 2 2 4 2 4
1 7 7 7 7 5 5 5 5 5 5
2 7 7 7 7 5 5 5 5 5 5
3 8 8 8 8 6 6 6 6 6 6
1 7 7 7 7 5 5 5 5 5 5
1 8 8 8 8 6 6 6 6 6 6
2 7 7 7 7 5 5 5 5 5 5
3 8 8 8 8 6 6 6 6 6 6
2
3 4 3 4 3 4
2 1 2
1 1 1 1
7 5 5
7 5 5
8 6 6
7 5 5
8 6 6
7 5 5
8 6 6
1 4
1 1 1
5 5
5 5
6 6
5 5
6 6
5 5
6 6
3 4 5 9
6 7 10 11 6 8 10 12 1 2
1 1 1 1 1 1
20 25 20 25 8 8
23 28 23 28 11 11
23 28 23 28 11 11
24 29 24 29 12 12
23 24 28 29 23 24 28 29 11 12 11 12
23 28 23 28 11 11
24 29 24 29 12 12
21 21 27 27 9 10
For register and immediate operands For memory operand
364
#xx:16 3
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (5)
Instruction Bcc d:8 Bcc d:16 BSR JMP (Condition) Condition false, branch not taken Condition true, branch taken Condition false, branch not taken Condition true, branch taken d:8 d:16 @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) JSR @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) LDM LINK NOP RTD RTE RTS SCB Condition false, branch not taken Count = -1, branch not taken Other than the above, branch taken SLEEP STM * n is the number of registers specified in the register list. Cycles preceding transition to powerdown mode 6 + 3n* 2n 2 #xx:8 #xx:16 Minimum mode Maximum mode #xx:8 #xx:16 Execution Cycles 3 7 3 7 9 9 7 6 7 8 9 9 9 10 6 + 4n* 6 7 2 9 9 13 15 8 3 4 8 2 2 2 4 6 2 2 2 2 2 2n 2 2 2 2 I J+K 2 5 3 6 4 5 5 5 5 6 5 5 5 6 2 2 3 1 4 5 4 4 4 3 3 6 0
365
Table A-7 Instruction Execution Cycles (6)
Instruction TRAPA TRAP/VS
(Condition) Minimum mode Maximum mode V = 0, trap not taken V = 1, trap taken, minimum mode V = 1, trap taken, maximum mode
Execution Cycles 17 22 3 18 23 5 9 8 15 13 12 13 13
I 6 10 6 10 2
J+K 4 4 1 4 4 1 6 5
UNLK PJMP PJSR PRTS PRTD #xx:8 #xx:16 @aa:24 @Rn @aa:24 @Rn
4 4 4 4 4
6 5 5 5 6
Table A-8 (a) Adjusted Value (Branch Instruction)
Instruction BSR, JMP, JSR, RTS, RTD, RTE TRAPA, PJMP, PJSR, PRTS, PRTD Bcc, SCB, TRAP/VS (When branches) Address even odd even odd Adjusted Value 0 1 0 1
Table A-8 (b) Adjusted Value (Other Instructions by Addressing Modes)
@(d:8, Rn)
Instruction
@aa:16
@aa:8
MOV.B #xx:8, MOVTPE, MOVFPE MOV.W #xx:16,
even odd even odd
1 1 2 0 0 0 1 0
1 1 0 2 0 1
1 1 2 0 1 0
1 1 2 0 1 0
1 1 2 0 1 0
1 1 0 2 0 1
1 1 2 0 1 0 0 0 0 0
Instruction other than above
even odd
366
#xx:16
Start address @Rn Rn
@(d:16, Rn)
@Rn+
@-Rn
#xx:8
Appendix B Register Field
B.1 Register Addresses and Bit Names
Addr. (last byte) H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F
Register Name Bit 7 P1DDR P17DDR P2DDR -- P1DR P17 P1DR -- P3DDR P37DDR P4DDR P47DDR P3DR P37 P4DR P47 P5DDR P57DDR P6DDR -- P5DR P57 P6DR -- P7DDR P77DDR -- -- P7DR P77 P8DR P87 TCR ICIE TCSR ICF FRC (H) FRC (L) OCRA (H) OCRA (L) OCRB (H) OCRB (L) ICR (H) ICR (L) -- -- -- -- -- -- -- -- -- -- -- --
Bit 6 P16DDR -- P16 -- P36DDR P46DDR P36 P46 P56DDR -- P56 -- P76DDR -- P76 P86 OCIEB OCFB
Bit 5 P15DDR -- P15 -- P35DDR P45DDR P35 P45 P55DDR -- P55 -- P75DDR -- P75 P85 OCIEA OCFA
Bit Names Bit 4 Bit 3 P14DDR P13DDR P24DDR P23DDR P14 P13 P24 P23 P34DDR P33DDR P44DDR P43DDR P34 P33 P44 P43 P54DDR P53DDR -- P63DDR P54 P53 -- P63 P74DDR P73DDR -- -- P74 P73 P84 P83 OVIE OEB OVF OLVLB
Bit 2 P12DDR P22DDR P12 P22 P32DDR P42DDR P32 P42 P52DDR P62DDR P52 P62 P72DDR -- P72 P82 OEA OLVLA
Bit 1 P11DDR P21DDR P11 P21 P31DDR P41DDR P31 P41 P51DDR P61DDR P51 P61 P71DDR -- P71 P81 CKS1 IEDG
Bit 0 P10DDR P20DDR P10 P20 P30DDR P40DDR P30 P40 P50DDR P60DDR P50 P60 P70DDR -- P70 P80 CKS0 CCLRA
Module Port 1 Port 2 Port 1 Port 2 Port 3 Port 4 Port 3 Port 4 Port 5 Port 6 Port 5 Port 6 Port 7 -- Port 7 Port 8
FRT 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Continued on next page)
Note: FRT1: Free-Running Timer channel 1
367
(Continued from preceding page) Addr. (last byte) H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF
Register Name Bit 7 TCR ICIE TCSR ICF FRC (H) FRC (L) OCRA (H) OCRA (L) OCRB (H) OCRB (L) ICR (H) ICR (L) -- -- -- -- -- -- -- -- -- -- -- -- TCR ICIE TCSR ICF FRC (H) FRC (L) OCRA (H) OCRA (L) OCRB (H) OCRB (L) ICR (H) ICR (L) -- -- -- -- -- -- -- -- -- -- -- --
Bit 6 OCIEB OCFB
Bit 5 OCIEA OCFA
Bit 4 OVIE OVF
Bit Names Bit 3 Bit 2 OEB OEA OLVLB OLVLA
Bit 1 CKS1 IEDG
Bit 0 CKS0 CCLRA
Module
FRT2 -- -- -- -- -- -- OCIEB OCFB -- -- -- -- -- -- OCIEA OCFA -- -- -- -- -- -- OVIE OVF -- -- -- -- -- -- OEB OLVLB -- -- -- -- -- -- OEA OLVLA -- -- -- -- -- -- CKS1 IEDG -- -- -- -- -- -- CKS0 CCLRA
FRT 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Continued on next page)
Notes: FRT2: Free-Running Timer channel 2 FRT3: Free-Running Timer channel 3
368
(Continued from preceding page) Addr. (last byte) H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF Notes: PWM1: PWM2: PWM3: TMR: SCI:
Register Name TCR DTR TCNT -- TCR DTR TCNT -- TCR DTR TCNT -- -- -- -- -- TCR TCSR TCORA TCORB TCNT -- -- -- SMR BRR SCR TDR SSR RDR -- --
Bit 7 OE
Bit 6 OS
Bit 5 --
Bit 4 --
Bit Names Bit 3 Bit 2 -- CKS2
Bit 1 CKS1
Bit 0 CKS0
Module PWM1
-- OE
-- OS
-- --
-- --
-- --
-- CKS2
-- CKS1
-- CKS0 PWM2
-- OE
-- OS
-- --
-- --
-- --
-- CKS2
-- CKS1
-- CKS0 PWM3
-- -- -- -- -- CMIEB CMFB
-- -- -- -- -- CMIEA CMFA
-- -- -- -- -- OVIE OVF
-- -- -- -- -- CCLR1 --
-- -- -- -- -- CCLR0 OS3
-- -- -- -- -- CKS2 OS2
-- -- -- -- -- CKS1 OS1
-- -- -- -- -- CKS0 OS0
--
TMR -- -- -- C/A TIE TDRE -- -- -- -- -- CHR RIE RDRF -- -- -- -- -- PE TE ORER -- -- -- -- -- O/E RE FER -- -- -- -- -- STOP -- PER -- -- -- -- -- -- -- -- -- -- -- -- -- CKS1 CKE1 -- -- -- -- -- -- CKS0 CKE0 SCI -- -- -- (Continued on next page)
Pulse-Width Modulation timer channel 1 Pulse-Width Modulation timer channel 2 Pulse-Width Modulation timer channel 3 8-Bit Timer Serial Communication Interface
369
(Continued from preceding page) Addr. (last byte) H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF
Register Name Bit 7 ADDRA (H) AD9 ADDRA (L) AD1 ADDRB (H) AD9 ADDRB (L) AD1 ADDRC (H) AD9 ADDRC (L) AD1 ADDRD (H) AD9 ADDRD (L) AD1 ADCSR ADF -- -- -- -- -- -- TCSR* OVF TCNT* -- -- -- -- --
Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- -- WT/IT -- -- --
Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- -- TME -- -- --
Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- -- -- -- -- --
Bit Names Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- -- -- -- -- --
Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- -- CKS2 -- -- --
Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- -- CKS1 -- -- --
Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- -- CKS0 -- -- --
Module
A/D
WDT
--
Notes: (Continued on next page) A/D: Analog-to-Digital converter WDT: Watchdog Timer * Read addresses are shown. Write addresses of both TCSR and TCNT are H'FFED. See section 13.2.3, "Notes on Register Access" for details.
370
(Continued from preceding page) Addr. (last byte) H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF
Register Name IPRA IPRB IPRC IPRD DTEA DTEB DTEC DTED WCR RAMCR MDCR SBYCR P1CR -- P9DDR P9DR
Bit 7 -- -- -- -- -- -- -- -- -- RAME -- SSBY -- -- P97DDR P97
Bit 5 IRQ0 FRT1 FRT3 SCI -- -- OCIB1 OCIA1 OCIB3 OCIA3 TXI RXI -- -- -- -- -- -- -- -- IRQ1E IRQ0E -- -- P96DDR P95DDR P96 P95
Bit 6
Bit Names Bit 3 -- -- -- -- IRQ0 -- ICI1 -- ICI3 -- -- -- -- WMS1 -- -- -- -- -- -- NMIEG BRLE -- -- P94DDR P93DDR P94 P93 Bit 4
Bit 1 Bit 0 IRQ1 FRT2 8 Bit Timer A/D -- -- IRQ1 OCIB2 OCIA2 ICI2 -- CMIB CMIA -- -- ADI WMS0 WC1 WC0 -- -- -- MDS2 MDS1 MDS0 -- -- -- -- -- -- -- -- -- P92DDR P91DDR P90DDR P92 P91 P90
Bit 2
Module
INTC
WSC RAM
Port 1 Port 9
Notes: INTC: Interrupt Controller WSC: Wait State Controller
371
B.2 Register Descriptions
Register name Acronym of the register
SYSCR1--System Control Register 1
Address to which the register is mapped
H'FEFC
Name of the on-chip supporting module
Port 1
Bit numbers Initial bit values
Bit
7 --
6 IRQ1E 0 R/W
5 IRQ0E 0 R/W
4 NMIEG 0 R/W
3 BRLE 0 R/W
2 -- 1 --
1 -- 1 --
0 -- 1 --
Initial value Read/Write
1 --
Names of the bits. Dashes (--) indicate reserved bits.
Type of access permitted R Read only W Write only R/W Both read and write
Bus Release Enable 0 P12 and P13 are I/O ports. 1 P12 is the BACK output pin. P13 is the BREQ input pin.
Full name of the bit
Nonmaskable Interrupt Edge 0 An NMI request is generated on the falling edge of the NMI pin input. 1 An NMI request is generated on the rising edge of the NMI pin input.
Functions of the bit settings
Interrupt Request 0 Enable 0 P15 is an I/O port; IRQ0 input is disabled. 1 P15 is the IRQ0 input pin.
Interrupt Request 1 Enable 0 P16 is an I/O port; IRQ1 input is disabled. 1 P16 is the IRQ1 input pin.
372
P1DDR--Port 1 Data Direction Register
Bit 7 6 5 4
H'FF80
3 2 1
Port 1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 1 Input/Output Selection 0 Input port 1 Output port P1DR--Port 1 Data Register
Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W
H'FF82
3 P13 0 R/W 2 P12 0 R/W 1 P11 -- R
Port 1
0 P10 -- R
373
P1CR--Port 1 Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 IRQ1E 0 R/W 5 IRQ0E 0 R/W 4 NMIEG 0 R/W
H'FFFC
3 BRLE 0 R/W 2 -- 1 -- 1 -- 1 --
Port 1
0 -- 1 --
Bus Release Enable 0 P12 and P13 are I/O ports. 1 P12 is the output pin and P13 is the input pin. Nonmaskable Interrupt Edge 0 An NMI request is generated on the falling edge of the NMI pin input. 1 An NMI request is generated on the rising edge of the NMI pin input. Interrupt Request 0 Enable 0 P15 is an I/O port; input is disabled. 1 P15 is the input pin. Interrupt Request 1 Enable 0 P16 is an I/O port; input is disabled. 1 P16 is the input pin.
P2DDR--Port 2 Data Direction Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4
H'FF81
3 2 1
Port 2
0
P24DDR P23DDR P22DDR P21DDR P20DDR 0 W 0 W 0 W 0 W 0 W
Port 2 Input/Output Selection 0 Input port 1 Output port
374
P2DR--Port 2 Data Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 P24 0 R/W
H'FF83
3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W
Port 2
0 P20 0 R/W
P3DDR--Port 3 Data Direction Register
Bit 7 6 5 4
H'FF84
3 2 1
Port 3
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 3 Input/Output Selection 0 Input port 1 Output port P3DR--Port 3 Data Register
Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W
H'FF86
3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W
Port 3
0 P30 0 R/W
P4DDR--Port 4 Data Direction Register
Bit 7 6 5 4
H'FF85
3 2 1
Port 4
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 4 Input/Output Selection 0 Input port 1 Output port
375
P4DR--Port 4 Data Register
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W
H'FF87
3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W
Port 4
0 P40 0 R/W
P5DDR--Port 5 Data Direction Register
Bit 7 6 5 4
H'FF88
3 2 1
Port 5
0
P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 5 Input/Output Selection 0 Input port 1 Output port P5DR--Port 5 Data Register
Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W
H'FF8A
3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W
Port 5
0 P50 0 R/W
P6DDR--Port 6 Data Direction Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FF89
3 2 1
Port 6
0
P63DDR P62DDR P61DDR P60DDR 0 W 0 W 0 W 0 W
Port 6 Input/Output Selection 0 Input port 1 Output port
376
P6DR--Port 6 Data Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FF8B
3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W
Port 6
0 P60 0 R/W
P7DDR--Port 7 Data Direction Register
Bit 7 6 5 4
H'FF8C
3 2 1
Port 7
0
P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 7 Input/Output Selection 0 Input port 1 Output port P7DR--Port 7 Data Register
Bit 7 P77 Initial value Read/Write 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W
H'FF8E
3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W
Port 7
0 P70 0 R/W
P8DR--Port 8 Data Register
Bit 7 P87 Read/Write R 6 P86 R 5 P85 R 4 P84 R
H'FF8F
3 P83 R 2 P82 R 1 P81 R
Port 8
0 P80 R
377
P9DDR--Port 9 Data Direction Register
Bit 7 6 5 4
H'FFFE
3 2 1
Port 9
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 9 Input/Output Selection 0 Input port 1 Output port
P9DR--Port 9 Data Register
Bit 7 P97 Initial value Read/Write 0 R/W 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W
H'FFFF
3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W
Port 9
0 P90 0 R/W
378
TCR--Timer Control Register
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FF90
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT1
0 CKS0 0 R/W
Clock Select 00 Internal clock source: o4 01 Internal clock source: o8 10 Internal clock source: o32 11 External clock source: counted on rising edge Output Enable A 0 Compare-A output is disabled. 1 Compare-A output is enabled. Output Enable B 0 Compare-B output is disabled. 1 Compare-B output is enabled. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Output Compare Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. Input Capture Interrupt Enable 0 Input capture interrupt is disabled. 1 Input capture interrupt is enabled.
379
TCSR--Timer Control/Status Register
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)*
H'FF91
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT1
0 CCLRA 0 R/W
Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by comparematch A. Input Edge Select 0 Count is captured on falling edge of input capture signal (FTI). 1 Count is captured on rising edge of input capture signal. 0 1 Output Level A Compare-match A causes 0 output. Compare-match A causes 1 output.
0 1 0 1 0 1 0
Output Level B Compare-match B causes 0 output. Compare-match B causes 1 output.
Timer Overflow Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. Set to 1 when FRC changes from H'FFFF to H'0000.
Output Compare Flag A Cleared from 1 to 0 when: 1. CPU reads OCFA = 1, then writes 0 in OCFA. 2. OCIA interrupt is served by DTC. Set to 1 when FRC = OCRA.
Output Compare Flag B Cleared from 1 to 0 when: 1. CPU reads OCFB = 1, then writes 0 in OCFB. 2. OCIB interrupt is served by DTC. 1 Set to 1 when FRC = OCRB. Input Capture Flag 0 Cleared from 1 to 0 when: 1. CPU reads ICF = 1, then writes 0 in ICF. * Only writing of a 0 to 2. ICI interrupt is served by DTC. clear the flag is enabled. 1 Set to 1 when input capture signal is received and FRC count is copied to ICR. 380
FRC (H and L)--Free-Running Counter
Bit 7 6 5 4
H'FF92, H'FF93
3 2 1
FRT 1
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value OCRA (H and L)--Output Compare Register A
Bit 7 6 5 4
H'FF94, H'FF95
3 2 1
FRT 1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Continually compared with FRC. OCFA is set to 1 when OCRA = FRC. OCRB (H and L)--Output Compare Register B
Bit 7 6 5 4
H'FF96, H'FF97
3 2 1
FRT 1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Continually compared with FRC. OCFB is set to 1 when OCRB = FRC. ICR (H and L)--Input Capture Register
Bit 7 6 5 4
H'FF98, H'FF99
3 2 1
FRT 1
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Contains FRC count captured when external input capture signal changes.
381
TCR--Timer Control Register
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FFA0
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT 2
0 CKS0 0 R/W
Note: Bit functions are the same as for FRT1.
TCSR--Timer Control/Status Register
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)*
H'FFA1
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT 2
0 CCLRA 0 R/W
Note: Bit functions are the same as for FRT1. * Only writing of a 0 to clear the flag is enabled.
FRC (H and L)--Free-Running Counter
Bit 7 6 5 4
H'FFA2, H'FFA3
3 2 1
FRT 2
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Note: Bit functions are the same as for FRT1.
382
OCRA (H and L)--Output Compare Register A
Bit 7 6 5 4
H'FFA4, H'FFA5
3 2 1
FRT 2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
OCRB (H and L)--Output Compare Register B
Bit 7 6 5 4
H'FFA6, H'FFA7
3 2 1
FRT 2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
ICR (H and L)--Input Capture Register
Bit 7 6 5 4
H'FFA8, H'FFA9
3 2 1
FRT 2
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for FRT1.
TCR--Timer Control Register
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FFB0
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT 3
0 CKS0 0 R/W
Note: Bit functions are the same as for FRT1.
383
TCSR--Timer Control/Status Register
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)*
H'FFB1
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT 3
0 CCLRA 0 R/W
Note: Bit functions are the same as for FRT1. * Only writing of 0 to clear the flag is enabled.
FRC (H and L)--Free-Running Counter
Bit 7 6 5 4
H'FFB2, H'FFB3
3 2 1
FRT 3
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Note: Bit functions are the same as for FRT1.
OCRA (H and L)--Output Compare Register A
Bit 7 6 5 4
H'FFB4, H'FFB5
3 2 1
FRT 3
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
384
OCRB (H and L)--Output Compare Register B
Bit 7 6 5 4
H'FFB6, H'FFB7
3 2 1
FRT 3
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
ICR (H and L)--Input Capture Register
Bit 7 6 5 4
H'FFB8, H'FFB9
3 2 1
FRT 3
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for FRT1.
385
TCR--Timer Control Register
Bit 7 OE Initial value Read/Write 0 R/W 6 OS 0 R/W 5 -- 1 -- 4 -- 1 --
H'FFC0
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W
PWM1
0 CKS0 0 R/W
000 001 010 011 100 101 110 111
Clock Select (Values When o = 10MHz) Internal ResoPW PW Clock Freq. lution Period Frequency o/2 200ns 50s 20kHz o/8 800ns 200s 5kHz o/32 3.2s 800s 1.25kHz o/128 12.8s 3.2ms 312.5kHz o/256 25.6s 6.4ms 156.3Hz o/1024 102.4s 25.6ms 39.1Hz o/2048 204.8s 51.2ms 19.5Hz o/4096 409.6s 102.4ms 9.8Hz
Output Select 0 Positive logic 1 Negative logic
Output Enable 0 PW output disabled; TCNT cleared to H'00 and stops. 1 PW output enabled; TCNT runs.
DTR--Duty Register
Bit 7 6 5 4
H'FFC1
3 2 1
PWM1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Pulse duty factor
386
TCNT--Timer Counter
Bit 7 6 5 4
H'FFC2
3 2 1
PWM1
0
Initial value Read/Write
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Count value (runs from H'00 to H'F9, then repeats from H'00)
* Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects
TCR--Timer Control Register
Bit 7 OE Initial value Read/Write 0 R/W 6 OS 0 R/W 5 -- 1 -- 4 -- 1 --
H'FFC4
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W
PWM2
0 CKS0 0 R/W
Note: Bit functions are the same as for PWM1.
DTR--Duty Register
Bit 7 6 5 4
H'FFC5
3 2 1
PWM2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for PWM1.
387
TCNT--Timer Counter
Bit 7 6 5 4
H'FFC6
3 2 1
PWM2
0
Initial value Read/Write
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Note: Bit functions are the same as for PWM1. * Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects
TCR--Timer Control Register
Bit 7 OE Initial value Read/Write 0 R/W 6 OS 0 R/W 5 -- 1 -- 4 -- 1 --
H'FFC8
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W
PWM3
0 CKS0 0 R/W
Note: Bit functions are the same as for PWM1.
DTR--Duty Register
Bit 7 6 5 4
H'FFC9
3 2 1
PWM3
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for PWM1.
388
TCNT--Timer Counter
Bit 7 6 5 4
H'FFCA
3 2 1
PWM3
0
Initial value Read/Write
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Note: Bit functions are the same as for PWM1. * Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects.
389
TCR--Timer Control Register
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W
H'FFD0
3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
TMR
0 CKS0 0 R/W
Clock Select 0 0 0 No clock source; timer stops. 0 0 1 Internal clock source: o8, counted on falling edge. 0 1 0 Internal clock source: o64, counted on falling edge. 0 1 1 Internal clock source: o1024, counted on falling edge. 1 0 0 No clock source; timer stops. 1 0 1 External clock source, counted on rising edge. 1 1 0 External clock source, counted on falling edge. 1 1 1 External clock source, counted on both rising and falling edges. Counter Clear Counter is not cleared. Cleared by compare-match A. Cleared by compare-match B. Cleared on rising edge of external reset input.
0 0 1 1
0 1 0 1
Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled.
390
TCSR--Timer Control/Status Register
Bit 7 CMFB Initial value Read/Write 0 R/(W)*1 6 CMFA 0 R/(W)*1 5 OVF 0 R/(W)*1 4 -- 1 --
H'FFD1
3 OS3*2 0 R/W 2 OS2*2 0 R/W 1 OS1*2 0 R/W
TMR
0 OS0*2 0 R/W
0 0 1 1
0 1 0 1
Output Select No change on compare-match A. Output 0 on compare-match A. Output 1 on compare-match A. Invert (toggle) output on compare-match A.
Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. Timer Overflow Flag 0 Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared from 1 to 0 when: 1. CPU reads CMFA = 1, then writes 0 in CMFA. 2. CMA interrupt is served by the DTC. 1 Set to 1 when TCNT = TCORA. Compare-Match Flag B 0 Cleared from 1 to 0 when: 1. CPU reads CMFB = 1, then writes 0 in CMFB. 2. CMB interrupt is served by the DTC. 1 Set to 1 when TCNT = TCORB.
*1 Only writing of 0 to clear the flag is enabled. *2 When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
391
TCORA--Time Constant Register A
Bit 7 6 5 4
H'FFD2
3 2 1
TMR
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The CMFA bit is set to 1 when TCORA = TCNT. TCORB--Time Constant Register B
Bit 7 6 5 4
H'FFD3
3 2 1
TMR
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The CMFB bit is set to 1 when TCORB = TCNT. TCNT--Timer Counter
Bit 7 6 5 4
H'FFD4
3 2 1
TMR
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value
392
SMR--Serial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FFD8
3 STOP 0 R/W 2 -- 1 -- 1 CKS1 0 R/W
SCI
0 CKS0 0 R/W
0 0 1 1
0 1 0 1
Clock Select o clock o/4 clock o/16 clock o/64 clock
Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-Bit data length 1 7-Bit data length Communication Mode 0 Asynchronous 1 Synchronous
393
BRR--Bit Rate Register
Bit 7 6 5 4
H'FFD9
3 2 1
SCI
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Constant that determines the baud rate SCR--Serial Control Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FFDA
3 -- 1 -- 2 -- 1 -- 1 CKE1 0 R/W
SCI
0 CKE0 0 R/W
Clock Enable 0 0 SCK pin is NOT USED. 1 SCK pin is used for output. Clock Enable 1 0 Internal clock 1 External clock, input at SCK pin Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt request (RXI) is disabled. 1 Receive interrupt request (RXI) is enabled. Transmit Interrupt Enable 0 Transmit interrupt request (TXI) is disabled. 1 Transmit interrupt request (TXI) is enabled.
394
TDR--Transmit Data Register
Bit 7 6 5 4
H'FFDB
3 2 1
SCI
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Transmit data
395
SSR--Serial Status Register
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)*
H'FFDC
3 PER 0 R/(W)* 2 -- 1 -- 1 -- 1 --
SCI
0 -- 1 --
Parity Error 0 Cleared from 1 to 0 when: 1. CPU reads PER = 1, then writes 0 in PER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a parity error occurs (parity of receive data does not match parity selected by bit). Framing Error 0 Cleared from 1 to 0 when: 1. CPU reads FER = 1, then writes 0 in FER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared from 1 to 0 when: 1. CPU reads ORER = 1, then writes 0 in ORER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared from 1 to 0 when: 1. CPU reads RDRF = 1, then writes 0 in RDRF. 2. RDR is read by the DTC. 3. The chip is reset or enters a standby mode. 1 Set to 1 when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared from 1 to 0 when: 1. CPU reads TDRE = 1, then writes 0 in TDRE. 2. The DTC writes data in TDR. 1 Set to 1 when: 1. The chip is reset or enters a standby mode. 2. Data is transferred from TDR to TSR. 3. CPU reads TDRE = 0, then clears 0 in TE. * Only writing of 0 to clear the flag is enabled.
396
RDR--Receive Data Register
Bit 7 6 5 4
H'FFDD
3 2 1
SCI
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Receive data ADDRn (H)--A/D Data Register n (High) H'FFE0, H'FFE2, H'FFE4, H'FFE6
Bit 7 AD9 Initial value Read/Write 0 R 6 AD8 0 R 5 AD7 0 R 4 AD6 0 R
(n = A, B, C, D)
3 AD5 0 R 2 AD4 0 R 1 AD3 0 R
A/D
0 AD2 0 R
Upper 8 bits of 10-bit A/D conversion result ADDRn (L)--A/D Data Register n (Low) H'FFE1, H'FFE3, H'FFE5, H'FFE7
Bit 7 AD1 Initial value Read/Write 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R
(n = A, B, C, D)
3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
Lower 2 bits of 10-bit A/D conversion result
397
ADCSR--A/D Control/Status Register
Bit 7 ADF Initial value Read/Write 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W
H'FFE8
3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W
A/D
0 CH0 0 R/W
CH2 CH1 CH0 0 0 0 1 0 1 0 1 1 0 0 0 1 1 1 0 1 1
Channel Select Single Mode Scan Mode AN0 AN0 AN1 AN0, AN1 AN2 AN0 to AN2 AN3 AN0 to AN3 AN4 AN4 AN5 AN4, AN5 AN6 AN4 to AN6 AN7 AN4 to AN7
Clock Select 0 Conversion time = 274 states 1 Conversion time = 138 states Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is halted. 1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to 0. 2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until 0 is written in this bit. A/D Interrupt Enable 0 The A/D interrupt request (ADI) is disabled. 1 The A/D interrupt request (ADI) is enabled. A/D End Flag 0 Cleared from 1 to 0 when: 1. The chip is reset or enters a standby mode. 2. CPU reads ADF = 1, then writes 0 in ADF. 3. DTC is served by ADI. 1 Set to 1 at the following times: 1. Single mode: at the completion of A/D conversion. 2. Scan mode: when all selected channels have been converted. * Only writing of 0 to clear the flag is enabled.
398
TCSR--Timer Status/Control Register
Bit 7 OVF Initial value Read/Write 0 R/(W)*3 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 --
H'FFEC*1, H'FFED*2
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W
WDT
0 CKS0 0 R/W
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Clock Select o/2 (51.2s)*4 o/32 (819.2s) o/64 (1.6ms) o/128 (3.3ms) o/256 (6.6ms) o/512 (13.1ms) o/2048 (52.4ms) o/4096 (104.9ms)
Timer Enable 0 Timer is disabled. * TCNT is initialized to H'00 and stopped. 1 Timer is enabled. * TCNT starts incrementing. * CPU interrupt request is enabled. Timer Mode Select 0 Interval timer mode (IRQ0 interrupt request) 1 Watchdog timer mode (NMI interrupt request)
Overflow Flag 0 Cleared from 1 to 0 when CPU reads OVF = 1, then wtites 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00.
*1 *2 *3 *4 Read address Write address Only writing of 0 to clear the flag is enabled. Times in parentheses are the times for TCNT to increment from H'00 to H'FF and change to H'00 again when o = 10MHz.
399
TCNT--Timer Counter
Bit 7 6 5 4
H'FFED
3 2 1
WDT
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value IPRA--Interrupt Priority Register A
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FFF0
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
IRQ0 interrupt priority level (0 to 7) IPRB--Interrupt Priority Register B
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
IRQ1 interrupt priority level (0 to 7) INTC
2 1 0
H'FFF1
3 -- 0 R 0 R/W 0 R/W
0 R/W
16-Bit FRT1 interrupt priority level (0 to 7)
16-Bit FRT2 interrupt priority level (0 to 7)
400
IPRC--Interrupt Priority Register C
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FFF2
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
16-Bit FRT3 interrupt priority level (0 to 7)
8-Bit timer interrupt priority level (0 to 7)
IPRD--Interrupt Priority Register D
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FFF3
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
SCI interrupt priority level (0 to 7)
A/D interrupt priority level (0 to 7)
IPRD--Interrupt Priority Register D
Bit 7 -- Initial value Read/Write 0 R/W 6 -- 0 R/W 5 -- 0 R/W 0 R/W 4
H'FFF4
3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W
INTC
0
0 R/W
IRQ0 0 Served by CPU 1 Served by DTC
IRQ1 0 Served by CPU 1 Served by DTC
401
DTEB--Data Transfer Enable Register B
Bit 7 -- Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4
H'FFF5
3 -- 0 R/W 0 R/W 0 R/W 2 1
INTC
0
0 R/W
16-Bit FRT channel 1
16-Bit FRT channel 2
ICI 0 Served by CPU 1 Served by DTC
OCIA 0 Served by CPU 1 Served by DTC
OCIB 0 Served by CPU 1 Served by DTC
ICI 0 Served by CPU 1 Served by DTC
OCIA 0 Served by CPU 1 Served by DTC OCIB 0 Served by CPU 1 Served by DTC
402
DTEC--Data Transfer Enable Register C
Bit 7 -- Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4
H'FFF6
3 -- 0 R/W 2 -- 0 R/W 0 R/W 1
INTC
0
0 R/W
16-Bit FRT channel 3
8-Bit timer
CMIA 0 Served by CPU 1 Served by DTC
CMIB 0 Served by CPU 1 Served by DTC
ICI 0 Served by CPU 1 Served by DTC
OCIA 0 Served by CPU 1 Served by DTC OCIB 0 Served by CPU 1 Served by DTC
403
DTED--Data Transfer Enable Register D
Bit 7 -- Initial value Read/Write 0 R/W 0 R/W 0 R/W 6 5 4 -- 0 R/W
H'FFF7
3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W
INTC
0
0 R/W
SCI
A/D converter
ADI 0 Served by CPU 1 Served by DTC
RXI 0 Served by CPU 1 Served by DTC
TXI 0 Served by CPU 1 Served by DTC
404
WCR--Wait-State Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFF8
3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W
WSC
0 WC0 1 R/W
Wait Count 1 and 0 0 0 No wait states (TW) are inserted. 0 1 1 Wait states are inserted. 1 0 2 Wait states are inserted. 1 1 3 Wait state is inserted.
Wait Mode Select 1 and 0 0 0 Programmable wait mode 0 1 No wait states are inserted, regardless of the wait count. 1 0 Pin wait mode 1 1 Pin auto-wait mode
RAMCR--RAM Control Register
Bit 7 RAME Initial value Read/Write 1 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFF9
3 -- 1 -- 2 -- 1 -- 1 -- 1 --
RAM
0 -- 1 --
RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is enabled.
405
MDCR--Mode Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FFFA
3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R
Mode Select Value input at mode pins * Initialized according to the inputs at pins MD2, MD1, and MD0.
SBYCR--Software Standby Control Register
Bit 7 SSBY Initial value Read/Write 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFFB
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Software Standby 0 SLEEP instruction causes transition to sleep mode. 1 SLEEP instruction causes transition to software standby mode.
406
Appendix C I/O Port Schematic Diagrams
C.1 Schematic Diagram of Port 1
Figure C-1 (a) to (g) gives a schematic view of the port 1 input/output circuits.
Reset R Q D P10 DDR C WP1D P10 RP1 Internal data bus (PDB8)
WP1D: Write to P1DDR RP1: Read Port 1
o
Figure C-1 (a) Schematic Diagram of Port 1, Pin P10
Table C-1 (a) Port 1 Port Read (Pin P10)
Setting DDR = 0 DDR = 1 Port Read Data Pin value o
Reset R Q D P11 DDR C WP1D P11 RP1
Internal data bus (PDB9)
WP1D: Write to P1DDR RP1: Read Port 1
E
Figure C-1 (b) Schematic Diagram of Port 1, Pin P11
407
Table C-1 (b) Port 1 Port Read (Pin P11)
Setting DDR = 0 DDR = 1 Port Read Data Pin value E
Reset R Q D Internal data bus (PDB10) P12 DDR C WP1D Reset R P12 Q D P12 DR C WP1 Mode 1, 2, 3, or 4
WP1D: Write to P1DDR WP1: Write to Port 1 RP1: Read Port 1
Port 1 control register, bit 3 BRLE Q
BACK
RP1
Figure C-1 (c) Schematic Diagram of Port 1, Pin P12
Table C-1 (c) Port 1 Port Read (Pin P12)
Mode 1,2,3,4 Setting BRLE = 1 BRLE =0 DDR = 0 DDR = 1 Port Read Data DR value Pin value DR value Pin value DR value
DDR = 0 DDR = 1
7
408
Reset R Q D Internal data bus (PDB11) P13 DDR C WP1D Reset P13 R Q D P13 DR C WP1 Mode 1, 2, 3, or 4
WP1D: Write to P1DDR WP1: Write to Port 1 RP1: Read Port 1
Port 1 control register, bit 3 BRLE Q
RP1
BREQ to CPU
Figure C-1 (d) Schematic Diagram of Port 1, Pin P13
Table C-1 (d) Port 1 Port Read (Pin P13)
Mode 1,2,3,4 Setting BRLE = 1 BRLE =0 DDR = 0 DDR = 1 Port Read Data Pin value Pin value DR value Pin value DR value
DDR = 0 DDR = 1
7
409
Reset R Q D Internal data bus (PDB12) P14 DDR C WP1D Reset P14 R Q D P14 DR C WP1 Mode 1, 2, 3, or 4
WP1D: Write to P1DDR WP1: Write to Port 1 RP1: Read Port 1
Wait-state control register, bit 3 WMS1 Q
RP1
WAIT to CPU
Figure C-1 (e) Schematic Diagram of Port 1, Pin P14
Table C-1 (e) Port 1 Port Read (Pin P14)
Mode 1,2,3,4 Setting WMS 1 = 1 WMS 1 =0 DDR = 0 DDR = 1 Port Read Data Pin value Pin value DR value Pin value DR value
DDR = 0 DDR = 1
7
410
Reset R Q D P1n DDR C WP1D Reset P1n R Q D P1n DR C WP1 Internal data bus (PDB13, PDB14)
WP1D: WP1: RP1: n:
Write to P1DDR Write to Port 1 Read Port 1 5 or 6
Port 1 control register, bits 5 and 6 IRQ 0 E or IRQ 1 E Q
RP1
IRQ0 , IRQ 1 to CPU
Figure C-1 (f) Schematic Diagram of Port 1, Pins P15 and P16
Table C-1 (f) Port 1 Port Read (Pins P15, P16)
Setting IRQ0E or IRQ1E IRQ0E or IRQ1E Port Read Data =1 DDR = 0 =0 DDR = 1 DR value Pin value Pin value
411
Reset R P17 DDR C WP1D Reset R P17 Q D P17 DR C WP1 Internal data bus (PDB15) Q D
WP1D: Write to P1DDR WP1: Write to Port 1 RP1: Read Port 1
8-Bit timer module Output enable 8-Bit timer output
RP1
Figure C-1 (g) Schematic Diagram of Port 1, Pin P17
Table C-1 (g) Port 1 Port Read (Pin P17)
Setting 8-bit timer output enable 8-bit timer output disable Port Read Data 8-bit timer output value Pin value DR value
DDR = 0 DDR = 1
412
C.2 Schematic Diagram of Port 2
Figure C-2 gives a schematic view of the port 2 input/output circuits.
Mode 1, 2, 3, or 4 Software standby Bus release S Q Reset R D
WP2D: WP2: RP2: n:
Write to P2DDR Write to Port 2 Read Port 2 0, 1, 2, 3, or 4
Mode 7
WP2D Reset R Q D
P2n
P2 n DR C Mode 1, 2, 3, or 4 WP2
RP2
Bus control signals
Figure C-2 Schematic Diagram of Port 2
Table C-2 Port 2 Port Read
Mode 1,2,3,4 7 DDR = 0 DDR = 1 Port Read Data DR value Pin value DR value
413
Internal data bus (PDB8 to PDB11)
P2 n DDR C
C.3 Schematic Diagram of Port 3
Figure C-3 gives a schematic view of the port 3 input/output circuits.
Data bus control Mode 1, 2, 3, or 4 Reset R Q Mode 7 D P3 n DDR C WP3 Mode 1, 2, 3, or 4 P3n Mode 7 Q Reset R D P3 n DR C WP3D
WP3D: WP3: RP3: n:
Write to P3DDR Write to Port 3 Read Port 3 0 to 7
Mode 1, 2, 3, or 4
RP3
External address read
Figure C-3 Schematic Diagram of Port 3
Table C-3 Port 3 Port Read
Mode 1,2,3,4 7 DDR = 0 DDR = 1 Port Read Data Always reads 1 Pin value DR value
414
Internal data bus (PDB8 to PDB15)
C.4 Schematic Diagram of Port 4
Figure C-4 gives a schematic view of the port 4 input/output circuits.
Mode 1, 2, 3, or 4 Software standby Bus release S Q Reset R D Internal data bus (PDB8 to PDB15)
WP4D: WP4: RP4: n:
Write to P4DDR Write to Port 4 Read Port 4 0 to 7
Mode 7
WP4D Reset R Q D
P4n
P4 n DR C Mode 1, 2, 3, or 4 WP4
RP4
Figure C-4 Schematic Diagram of Port 4
Table C-4 Port 4 Port Read
Mode 1,2,3,4 7 DDR = 0 DDR = 1 Port Read Data DR value Pin value DR value
415
Internal address bus (IAB0 to IAB7)
P4 n DDR C
C.5 Schematic Diagram of Port 5
Figure C-5 gives a schematic view of the port 5 input/output circuits.
Mode 1, 2, 3, or 4 Software standby Mode 1 or 3 Bus release MOS pull-up S Q Reset R D Internal data bus (PDB8 to PDB15) WP5D: WP5: RP5: n: Internal address bus (IAB8 to IAB15) Write to P5DDR Write to Port 5 Read Port 5 0 to 7
P5 n DDR C Mode 7 P5n WP5D Reset R Q D P5 n DR C Mode 1, 2, 3, or 4 WP5
RP5
Figure C-5 Schematic Diagram of Port 5
Table C-5 Port 5 Port Read
Mode 1,3 2,4,7 DDR = 0 DDR = 1 Port Read Data DR value Pin value DR value
416
C.6 Schematic Diagram of Port 6
Figure C-6 gives a schematic view of the port 6 input/output circuits.
Mode 3 or 4 Software standby Mode 3 Bus release MOS pull-up S Q Reset R D Internal data bus (PDB8 to PDB15) WP6D: WP6: RP6: n: Internal address bus (IAB16 to IAB19) Write to P6DDR Write to Port 6 Read Port 6 0 to 3
P6 n DDR C Mode 1, 2, or 7 P6n WP6D Reset R Q D P6 n DR C Mode 3 or 4 WP6
RP6
Figure C-6 Schematic Diagram of Port 6
Table C-6 Port 6 Port Read
Mode 3 1,2,4,7 DDR = 0 DDR = 1 Port Read Data DR value Pin value DR value
417
C.7 Schematic Diagram of Port 7
Figure C-7 (a) to (e) gives a schematic view of the port 7 input/output circuits.
Reset R1 Q D P70 DDR C WP7D Reset R P70 Q D P70 DR C WP7
WP7D: Write to P7DDR WP7: Write to Port 7 RP7: Read Port 7
Internal data bus (PDB8) 8-Bit timer module
RP7
Input clock
Figure C-7 (a) Schematic Diagram of Port 7, Pin P70
Table C-7 (a) Port 7 Port Read (Pin P70)
Setting DDR = 0 DDR = 1 Port Read Data Pin value DR value
418
Reset R1 Q D Internal data bus (PDB9 to 10) P7n DDR C WP7D Reset R P7n Q D P7n DR C WP7 WP7D: WP7: RP7: n: Write to P7DDR Write to Port 7 Read Port 7 1 or 2
Free-running timer module
RP7
Input capture signal
Figure C-7 (b) Schematic Diagram of Port 7, Pins P71 and P72
Table C-7 (b) Port 7 Port Read (Pins P71, P72)
Setting DDR = 0 DDR = 1 Port Read Data Pin value DR value
419
Reset R1 Q D Internal data bus (PDB11) P73 DDR C WP7D Reset R P73 Q D P73 DR C WP7
WP7D: Write to P7DDR WP7: Write to Port 7 RP7: Read Port 7
RP7 8-Bit timer module Counter reset input Free-running timer module Input capture signal
Figure C-7 (c) Schematic Diagram of Port 7, Pin P73
Table C-7 (c) Port 7 Port Read (Pin P73)
Setting DDR = 0 DDR = 1 Port Read Data Pin value DR value
420
Reset R Q D P7n DDR C WP7D Reset R P7n Q D P7n DR C WP7 Internal data bus (PDB12 to PDB14)
WP7D: WP7: RP7: n:
Write to P7DDR Write to Port 7 Read Port 7 4, 5 or 6
Free-running timer module Output enable Output compare output
RP7
Counter clock output
Figure C-7 (d) Schematic Diagram of Port 7, Pins P74, P75 and P76
Table C-7 (d) Port 7 Port Read (Pins P74 - P76)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data Output compare output value Pin value DR value
421
Reset Q R1 D Internal data bus (PDB15)
WP7D: Write to P7DDR WP7: Write to Port 7 RP7: Read Port 7
P77 DDR C WP7D Reset R P77 Q D P77 DR C WP7
Free-running timer module Output enable Output compare output
RP7
Figure C-7 (e) Schematic Diagram of Port 7, Pin P77
Table C-7 (e) Port 7 Port Read (Pin P77)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data Output compare output value Pin value DR value
422
C.8 Schematic Diagram of Port 8
Figure C-8 gives a schematic view of the port 8 input circuits.
Internal data bus (PDB8 to PDB15)
RP8: Read Port 8 n: 0 to 7
RP8 P8n
A/D converter module Input multiplexer
Figure C-8 Schematic Diagram of Port 8
423
C.9 Schematic Diagram of Port 9
Figure C-9 (a) to (e) gives a schematic view of the port 9 input/output circuits.
Reset Q D Internal data bus (PDB8, PDB9) R P9 n DDR C WP9D Reset R P9n Q D P9 n DR C WP9
WP9D: WP9: RP9: n:
Write to P9DDR Write to Port 9 Read Port 9 0 or 1
Free-running timer module Output enable Output compare output
RP9
Figure C-9 (a) Schematic Diagram of Port 9, Pins P90 and P91
Table C-9 (a) Port 9 Port Read (Pins P90, P91)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data Output compare output value Pin value DR value
424
Reset R Q D P9 n DDR C WP9D Reset R P9n Q D P9 n DR C WP9 Internal data bus (PDB10 to PDB12)
WP9D: WP9: RP9: n:
Write to P9DDR Write to Port 9 Read Port 9 2, 3, or 4
PWM timer module Output enable PWM 1 , PWM 2 , or PWM 3 output
RP9
Figure C-9 (b) Schematic Diagram of Port 9, Pins P92, P93 and P94
Table C-9 (b) Port 9 Port Read (Pins P92 - P94)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data PWM 1, 2, 3 output value Pin value DR value
425
Reset R Q D Internal data bus (PDB13) P9 5 DDR C WP9D Reset R P95 Q D P9 5 DR C WP9
WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9
SCI timer module Output enable Serial transfer data
RP9
Figure C-9 (c) Schematic Diagram of Port 9, Pin P95
Table C-9 (c) Port 9 Port Read (Pin P95)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data Serial transfer data Pin value DR value
426
Reset R Q D P96 DDR C WP9D WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 Internal data bus (PDB14) SCI timer module Input enable Serial receive data
P96
Reset R Q D P96 DR C WP9
RP9
Fig. C-9 (d)
Figure C-9 (d) Schematic Diagram of Port 9, Pin P96
Table C-9 (d) Port 9 Port Read (Pin P96)
Setting Output enable Output disable DDR = 0 DDR = 1 Port Read Data Serial transfer data Pin value DR value
427
Reset R Q D P97 DDR C WP9D Internal data bus (PDB15)
WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9
Reset R P97 Q D P97 DR C WP9
SCI timer module
Clock input enable Clock output enable Clock output
RP9
Clock input
Figure C-9 (e) Schematic Diagram of Port 9, Pin P97
Table C-9 (e) Port 9 Port Read (Pin P97)
Setting Clock input enable Clock output enable Clock input/output enable Port Read Data Input clock value Output clock value Pin value DR value
DDR = 0 DDR = 1
428
429
Appendix D Memory Map
Expanded maximum mode Mode 3
H'00000 H'00000 H'0000
Expanded maximum mode Mode 2 Vector tables
H'0017F H'00180 H'0017F H'00180 H'00BF H'00C0
Single-chip mode Mode 7 Vector tables On-chip ROM 32K bytes
H'7FFF
Mode 1 Vector tables External memory
H'07FFF H'08000
Mode 4 Vector tables On-chip ROM 32K bytes
H'0000
H'0000
Vector tables On-chip ROM 32K bytes
H'00BF H'00C0
H'00BF H'00C0
External memory
H'7FFF H'8000
Page 0
External memory
Page 0 Page 0 Page 0 H'0FB7F H'0FB80 H'0FB7F H'0FB80
External memory
Page 0
H'FB7F H'FB80 On-chip RAM 1K byte
H'0FF7F H'0FF80 H'0FF7F H'0FB80
H'FB7F H'FB80
H'FB80
On-chip RAM 1K byte On-chip RAM 1K byte On-chip RAM 1K byte
On-chip RAM 1K byte
H'FF7F H'FF80
430
Register field 128 bytes
H'0FFFF H'10000 Page 1 H'1FFFF H'1FFFF H'0FFFF H'10000
H'FF7F H'FF80 Register field 128 bytes
H'FF7F H'FF80
Register field 128 bytes
Register field 128 bytes
H'FFFF Page 1
Register field 128 bytes
H'FFFF
H'FFFF
External memory
External memory
H'F0000
H'F0000
Page 15
Page 15
H'FFFFF
H'FFFFF
Appendix E Pin State
E.1 Port State of Each Pin State
Table E-1 Port State
Hardware Port Pin Name P17 to P12 WAIT, BREQ, BACK P11/E P10/o Mode Reset 1 3 4 7 1 2 3 4 7 P24 to P20 WR, RD, DS, R/W, AS 1 2 3 4 7 P37 to P30 D7 to D0 1 2 3 4 7 P47 to P40 A7 to A0 1 2 3 4 7 P57 to P50 A15 to A8 1 2 3 4 7 T L T L T T keep T T*6 T T*6 keep keep L
*5
Standby Mode
Software Standby mode Sleep Mode
Bus-right
Program Execution Input/Output port or Control signal Input/
Release Mode State (Normal Operation)
TMO, IRQ1, IRQ0 2 T T keep*1 keep*2 (DDR = 1) Clock output T o=H E=L (DDR = 0) T H T H keep*3 keep (DDR = 1) (DDR = 0) T keep*4 --(DDR = 1) (DDR = 0) T ---
Output Input/Output port (DDR = 1) (DDR = 0) Input port WR, RD, DS,
Clock output Clock output Clock output
T
R/W, AS
T
keep T
keep T
--T
Input/Output port D7 to D0
T
T keep keep L --T Input/Output port A7 to A0
L T
T
--T' T*6 T T*6 ---
Input/Output port A15 to A8 Address/Input port A15 to A8 Address/Input port Input/Output port
L
*5
keep
431
Table E-1 Port State (cont)
Hardware Port Pin Name P63 to P60 A19 to A16 Mode Reset 1 2 3 4 7 P77 to P70 1 2 3 4 7 P87 to P80 1 2 3 4 7 P97 to P90 1 2 3 4 7 T T keep*2 keep keep Input/Output port T T T T T Input port T T keep*2 keep keep Input port T L T T Standby Mode Software Standby mode Sleep Mode keep T T*6 keep keep L
*5
Bus-right
Program Execution
Release Mode State (Normal Operation) keep T T*6 --Input/Output port A19 to A16 Address/Input port Input/Output port
keep
H: "High" = High level L: "Low" = Low level T: High Impedance keep: If DDR = 0 and DR = 1 in port 5 and 6, Pull-up MOS holds on-state. Notes: *1 8 Bit Timer is reset, so P17 becomes input or output port controlled by DDR and DR. Also P12 goes to the high impedance state when it is programmed as BACK output. *2 On-chip supporting modules are reset. So these pins become input or output ports controlled by DDR and DR. *3 BREQ can be accepted and BACK goes LOW. *4 BACK outputs LOW. *5 The pins programmed as address bus output LOW and others programmed as input are at the high impedance state. If DDR = 0 and DR = 1, the pull-up MOS's keep ON state. *6 If DDR = 0 and DR = 1, the pull-up MOS's keep ON state.
432
Table E-2 Pull-Up MOS State
Port P57 to P50 A15 to A8 Mode 1 2 3 4 7 1 2 3 4 7 Reset OFF Hardware Standby Mode OFF Other Operating State* OFF ON/OFF OFF ON/OFF ON/OFF OFF ON/OFF
P57 to P50 A15 to A8
OFF
OFF
OFF: Pull-up MOS is always OFF. ON/OFF: Pull-up MOS holds on-state only when DDR = "0" and DR = 1. * Including Software Standby Mode
433
E.2 Pin Status in the Reset State
1. Mode 1 Figures E-1 and E-2 show how the pin states change when the RES pin goes Low during external memory access in mode 1. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance state. The address bus and the R/W signal are initialized 1.5 o clock periods after the Low state of the RES pin is sampled. All address bus signals are made Low. The R/W signal is made High. The clock output pins P10/o and P11/E are initialized 0.5 o clock periods after the Low state of the RES pin is sampled. Both pins are initialized to the output state.
434
ZTAT Versions
External memory access
T1 P10 / o*
T2
T3
RES
Internal reset signal
A15 to A0
H'0000
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write) High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-1 Reset during Memory Access (Mode 1)
435
Masked-ROM Versions
External memory access
T1 P10 / o*
T2
T3
RES
Internal reset signal
A15 to A0
H'0000
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write)
High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-2 Reset during Memory Access (Mode 1)
436
2. Mode 2 Figures E-3 and E-4 show how the pin states change when the RES pin goes Low during external memory access in mode 2. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance state. Pins P57/A15 to P50/A8 of the address bus are initialized as input ports. Pins A7 to A0 of the address bus and the R/W signal are initialized 1.5 o clock periods after the Low state of the RES pin is sampled. Pins A7 to A0 are made Low. The signal is made High. The clock output pins P10/o and P11/E are initialized 0.5 o clock periods after the Low state of the RES pin is sampled. Both pins are initialized to the output state.
437
ZTAT Versions
External memory access
T1 P10 / o*
T2
T3
RES
Internal reset signal
A7 to A0
H'00
High impedance P57 /A15 to P5 0 to A 8
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write) High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-3 Reset during Memory Access (Mode 2)
438
Masked-ROM Versions
External memory access
T1 P10 / o*
T2
T3
RES
Internal reset signal
A7 to A 0
H'00
High impedance P57 /A15 to P5 0/A8
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write)
High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-4 Reset during Memory Access (Mode 2)
439
3. Mode 3 Figures E-5 and E-6 show how the pin states change when the RES pin goes Low during external memory access in mode 3. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance state. The address bus and the signal are initialized 1.5 o clock periods after the Low state of the RES pin is sampled. All address bus signals are made Low. The R/W signal is made High. The clock output pins P10/o and P11/E are initialized 0.5 o clock periods after the Low state of the RES pin is sampled. Both pins are initialized to the output state.
440
ZTAT Version
External memory access
T1 P10 / o*
T2
RES
Internal reset signal
A19 to A0
H'00000
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write)
High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-5 Reset during Memory Access (Mode 3)
441
Masked-ROM Version
External memory access
T1 P10 / o*
T2
RES
Internal reset signal
A19 to A0
H'0000
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write)
High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-6 Reset during Memory Access (Mode 3)
442
4. Mode 4 Figures E-7 and E-8 show how the pin states change when the RES pin goes Low during external memory access in mode 4. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance state. Pins P57/A15 to P50/A8 of the address bus and pins P63/A19 to P60/A16 of the page address bus are initialized as input ports. Pins A7 to A0 of the address bus and the R/W signal are initialized 1.5 o clock periods after the Low state of the RES pin is sampled. Pins A7 to A0 are made Low. The R/W signal is made High. The clock output pins P10/o and P11/E are initialized 0.5 o clock periods after the Low state of the RES pin is sampled. Both pins are initialized to the output state.
443
ZTAT Versions
T1 P10 / o*
T2
T3
T1
RES
Internal reset signal
A7 to A0
H'00
P63 /A19 to P6 0 to A16 and P57 /A15 to P5 0 /A8
High impedance
R/W
AS, RD and DS (read)
WR and DS (write)
D7 to D0 (write)
High impedance
I/O ports
High impedance
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-7 Reset during Memory Access (Mode 4)
444
Masked-ROM Versions
T1 P10 / o*
T2
T3
T1
RES
Internal reset signal
A7 to A0
H'00
P63 /A19 to P6 0/A16, P57 /A15 to P5 0 /A8
High impedance
R/W
AS, RD and DS (read)
WR and DS (write)
High impedance D7 to D0 (write)
High impedance I/O ports
*
The dotted line indicates that P10/o is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Figure E-8 Reset during Memory Access (Mode 4)
445
5. Mode 7 Figures E-9 and E-10 show how the pin states change when the RES pin goes Low in mode 7. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The clock output pins P10/o and P11/E are initialized 0.5 o clock periods after the Low state of the RES pin is sampled. Both pins are initialized to the output state. ZTAT Versions
P10 / o*
P10 / E*
RES
Internal reset signal
High impedance I/O ports
*
The dotted line indicates that P10/o and P10/E are input port if the corresponding DDR bit is 0, but clock output pins if the DDR bit is 1.
Figure E-9 Reset during Memory Access (Mode 7)
446
Masked-ROM Versions
P10 / o*
P10 /E*
RES
Internal reset signal
High impedance I/O ports
*
The dotted line indicates that P10/o and P10/E are input port if the corresponding DDR bit is 0, but clock output pins if the DDR bit is 1.
Figure E-10 Reset during Memory Access (Mode 7)
447
Appendix F Timing of Entry to and Recovery from Hardware Standby Mode
Timing of Entry to Hardware Standby Mode (1) To preserve RAM contents, drive the RES signal line low 10 system clock cycles before the fall of the STBY signal. The RES signal can rise any time after STBY goes low. The minimum necessary time from STBY low to RES high is 0 ns.
STBY t1 RES t2
(2) When it is not necessary to preserve RAM contents, RES need not be driven low as in (1).
Timing of Exit from Hardware Standby Mode Drive the RES signal line low approximately 100 ns before the rise of the STBY signal.
STBY t = 100ns RES tOSC
449
Appendix G Package Dimensions
Figure G-1 shows the dimensions of the CP-84 package. Figure G-2 shows the dimensions of the CG-84 package. Figure G-3 shows the dimensions of the FP-80A package.
Figure G-1 Package Dimensions (CP-84)
Figure G-2 Package Dimensions (CG-84)
451
Figure G-3 Package Dimensions (FP-80A)
452

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